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data sheet february 2004 ambassador ? t8110l h.100/h.110 switch 1 introduction the t8110l is the newest addition to the ambassa- dor series of tdm switching and backlane intercon- nect standard products. the t8110l can switch 4096 simultaneous time slots with 32 bidirectional local streams and 32 bidirectional h.100/h.110 streams. the t8110l has all the features of the t810x devices. additionally, the t8110l has more robust clocking fallback abilities and is pin compatible with the t8110. (the full version of the t8110 has a pci and minbridge interface.) 1.1 features ! 4,096-connection unified switch ! full h.100/h.110 support (32 data lines, all clock modes) ! 32 local i/o lines (2, 4, 8, or 16 mbits/s) ! microprocessor interface: motorola ? / intel ? modes ! interrupt controller with external inputs ! eight independent general-purpose i/o lines ! eight independently programmed framing signals ! four local clocks ! t1/e1 rate adaptation ! two clock-fallback modes ! stratum 4/4e and at&t ? 62411 mtie compliant ! incorporates 38 h.100 and 34 h.110 termination resistors ! subrate switching of 4 bits, 2 bits, or 1 bit ! backward compatible to all t810x devices ! pin compatible with t8110 ! jtag/boundary-scan testing support ! bsdl files available ! assists h.110 hot swap ! single 3.3 v supply with 5 v tolerant inputs and ttl compatible outputs ! 272 pbga package ! evaluation boards available
table of contents contents page 2 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 1 introduction .................................................................................................................. ....................................... 1 1.1 features.................................................................................................................... ................................1 2 pin description ............................................................................................................... ...................................10 2.1 interface signals ........................................................................................................... ..........................10 2.2 t8110l pinout information ................................................................................................... ..................12 2.3 special buffer requirements ................................................................................................. .................20 2.3.1 h1x0 bus signal internal pull-up/pull-down ..............................................................................20 2.3.2 local bus signal internal pull-up ......................................................................................... ......20 3 main architectural features ................................................................................................... ...........................21 3.1 t8110l architecture ......................................................................................................... ......................21 4 microprocessor interface ...................................................................................................... ............................22 4.1 intel / motorola protocol selector............................................................................................................. .22 4.2 word/byte addressing selector............................................................................................... ...............22 4.3 access via the microprocessor bus ........................................................................................... ............23 4.3.1 microprocessor interface register map ..................................................................................... .24 4.3.2 register space access ..................................................................................................... ..........28 4.3.3 connection memory space access ............................................................................................ 28 4.3.4 data memory space access.................................................................................................. .....29 5 operating control and status .................................................................................................. .........................30 5.1 control registers ........................................................................................................... .........................30 5.1.1 reset registers ........................................................................................................... ...............30 5.1.2 master output enable register............................................................................................. ......31 5.1.3 connection control?data memory selector register ...............................................................32 5.1.4 general clock control (phase alignment, fallback, watchdogs) register ................................33 5.1.5 phase alignment select register ........................................................................................... ....33 5.1.6 fallback control register................................................................................................. ...........33 5.1.7 fallback type select register ............................................................................................. .......34 5.1.8 fallback trigger registers ................................................................................................ ..........35 5.1.9 watchdog select, c8, and netref registers...........................................................................36 5.1.10 watchdog en register ..................................................................................................... ..........37 5.1.11 failsafe control registers............................................................................................... ............38 5.2 error and status registers .................................................................................................. ...................39 5.2.1 clock errors .............................................................................................................. ..................40 5.2.1.1 transient clock errors registers.................................................................................40 5.2.1.2 latched clock error register ......................................................................................41 5.2.2 system status ............................................................................................................. ................42 5.2.2.1 clock fallback status register....................................................................................42 5.2.2.2 device identification registers ....................................................................................43 5.2.2.3 system device errors..................................................................................................43 6 clock architecture ............................................................................................................ .................................44 6.1 clock input control registers ............................................................................................... ..................45 6.1.1 main input selector register.............................................................................................. .........45 6.1.2 main divider register..................................................................................................... .............46 6.1.3 analog pll1 (apll1) input selector register............................................................................46 6.1.4 apll1 rate register ....................................................................................................... ...........47 6.1.5 main inversion select register ............................................................................................ .......47 6.1.6 resource divider register ................................................................................................. .........48 6.1.7 analog pll2 (apll2) rate register ......................................................................................... .48 6.1.8 lref input select registers............................................................................................... ........49 6.1.9 dpll1 input selector ...................................................................................................... ............50
table of contents (continued) contents page agere systems inc. 3 february 2004 ambassador t8110l h.100/h.110 switch data sheet 6.1.9.1 dpll1 rate register...................................................................................................50 6.1.10 dpll2 input selector ..................................................................................................... .............50 6.1.10.1 dpll2 rate register...................................................................................................5 1 6.1.11 netref1 registers........................................................................................................ ............51 6.1.12 netref2 registers........................................................................................................ ............52 6.2 clock output control registers .............................................................................................. ................53 6.2.1 master output enables register ............................................................................................ .....53 6.2.2 clock output format registers............................................................................................. ......54 6.2.3 tclk and l_scx select registers ........................................................................................... ..55 6.3 clock register access....................................................................................................... .....................57 6.4 clock circuit operation?apll1 ............................................................................................... .............57 6.4.1 main clock selection, bit clock, and frame ...............................................................................5 7 6.4.1.1 watchdog timers ........................................................................................................5 8 6.4.1.2 frame center sampling ..............................................................................................59 6.4.1.3 lref pair polarity configuration.................................................................................60 6.4.2 main and resource dividers ................................................................................................ .......61 6.4.3 dpll1 ..................................................................................................................... ....................61 6.4.4 reference selector ........................................................................................................ .............61 6.4.5 internal clock generation ................................................................................................. ..........61 6.4.5.1 phase alignment ......................................................................................................... 62 6.5 clock circuit operation, apll2 .............................................................................................. ................63 6.5.1 dpll2 ..................................................................................................................... ....................63 6.6 clock circuit operation, ct_netref generation............................................................................... ..63 6.6.1 netref source select ...................................................................................................... ........63 6.6.2 netref divider............................................................................................................ ..............63 6.7 clock circuit operation?fallback and failsafe ............................................................................... ......64 6.7.1 clock fallback............................................................................................................ .................64 6.7.1.1 fallback events ......................................................................................................... ..64 6.7.1.2 fallback scenarios?fixed vs. rotating secondary....................................................65 6.7.1.3 h-bus clock enable/disable on fallback ....................................................................68 6.7.2 clock failsafe ............................................................................................................ .................70 6.7.2.1 failsafe events ......................................................................................................... ...70 7 frame group and fg i/o ........................................................................................................ ..........................72 7.1 frame group control registers............................................................................................... ...............72 7.1.1 fgx lower and upper start registers ....................................................................................... .72 7.1.2 fgx width registers ....................................................................................................... ............73 7.1.3 fgx rate registers ........................................................................................................ ............73 7.2 fg7 timer option ............................................................................................................ .......................74 7.2.1 fg7 counter (low and high byte) registers..............................................................................74 7.3 fgio control registers ...................................................................................................... ....................75 7.3.1 fgio data register ........................................................................................................ ............75 7.3.2 fgio read mask register................................................................................................... .......75 7.3.3 fgio r/w register ......................................................................................................... ............76 7.4 fg circuit operation........................................................................................................ .......................77 7.4.1 frame group 8 khz reference generation ................................................................................78 7.4.2 fgio general-purpose bits ................................................................................................. .......79 7.4.3 programmable timer (fg7 only)............................................................................................. ...79 7.4.4 fg external interrupts.................................................................................................... .............79 7.4.5 fg diagnostic test point observation...................................................................................... ..79 8 general-purpose i/o ........................................................................................................... ..............................80 8.1 gpio control registers ...................................................................................................... ....................80
table of contents (continued) contents page 4 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 8.1.1 gpio data register ........................................................................................................ ............80 8.1.2 gpio read mask register ................................................................................................... ......81 8.1.3 gpio r/w register......................................................................................................... ............81 8.1.4 gpio override register .................................................................................................... ..........82 8.2 gp circuit operation........................................................................................................ .......................82 8.2.1 gpio general-purpose bits................................................................................................. .......83 8.2.2 gp dual-purpose bits gpio (override)...................................................................................... 83 8.2.2.1 gp h.110 clock master indicators (gp0, gp1 only) ..................................................83 8.2.3 gp external interrupts .................................................................................................... ............83 8.2.4 gp diagnostic test point observation ...................................................................................... .83 9 stream rate control ........................................................................................................... ..............................84 9.1 h-bus stream rate control registers......................................................................................... ...........85 9.1.1 h-bus rate registers ...................................................................................................... ...........85 9.2 l-bus stream rate control registers ......................................................................................... ...........85 9.2.1 l-bus rate registers ...................................................................................................... ............85 9.2.2 l-bus 16.384 mbits/s operation ............................................................................................ .....86 9.2.3 16.384 mbits/s local i/o superrate ........................................................................................ ....88 9.2.4 16.384 mbits/s local i/o superrate ........................................................................................ ....89 10 error reporting and interrupt control ........................................................................................ .......................90 10.1 interrupt control registers................................................................................................ ......................90 10.1.1 interrupts via external fg[7:0] registers ................................................................................ ...90 10.1.1.1 fgio interrupt pending register.................................................................................90 10.1.2 interrupts via external gp[7:0] .......................................................................................... .........92 10.1.2.1 gpio interrupt pending register.................................................................................92 10.1.2.2 gpio edge/level and gpio polarity registers ..........................................................93 10.1.3 interrupts via internal system errors .................................................................................... ......93 10.1.4 system interrupt pending high/low registers ...........................................................................94 10.1.5 system interrupt enable high/low registers .............................................................................95 10.1.6 interrupts via internal clock errors ..................................................................................... ........96 10.1.7 clock interrupt pending high/low registers ..............................................................................9 7 10.1.8 clock interrupt enable high/low registers ................................................................................ 98 10.1.9 interrupt servicing registers............................................................................................ ...........99 10.1.9.1 arbitration control register .........................................................................................99 10.1.9.2 syserr and clkerr output select register ..........................................................99 10.1.9.3 interrupt in-service registers....................................................................................101 10.2 error reporting and interrupt controller circuit operation ................................................................. ..103 10.2.1 externally sourced interrupts via fg[7:0], gp[7:0] ..................................................................104 10.2.2 internally sourced system error interrupts ............................................................................... 104 10.2.3 internally sourced clock error interrupts ................................................................................ ..104 10.2.4 arbitration of pending interrupts ........................................................................................ .......104 10.2.4.1 arbitration off ........................................................................................................ ....104 10.2.4.2 flat arbitration ....................................................................................................... ....104 10.2.4.3 tier arbitration ....................................................................................................... ....104 10.2.4.4 pre-empting disabled................................................................................................105 10.2.4.5 pre-empting enabled ................................................................................................105 10.2.5 clkerr output............................................................................................................ ............105 10.2.6 syserr output ............................................................................................................ ...........105 10.2.7 system handling of interrupts............................................................................................ .......105 11 test and diagnostics ......................................................................................................... .............................106 11.1 diagnostics control registers .............................................................................................. ................106 11.1.1 fg testpoint enable register............................................................................................. ......106
table of contents (continued) contents page agere systems inc. 5 february 2004 ambassador t8110l h.100/h.110 switch data sheet 11.1.2 gp testpoint enable register ............................................................................................. .....108 11.1.3 state counter modes registers ............................................................................................ ....110 11.1.4 miscellaneous diagnostics low register..................................................................................1 10 11.1.5 miscellaneous diagnostic registers ....................................................................................... ..111 11.2 diagnostic circuit operation ............................................................................................... ..................112 12 connection control ........................................................................................................... ..............................113 12.1 programming interface ...................................................................................................... ...................113 12.1.1 connection memory programming ...........................................................................................1 13 12.2 switching operation........................................................................................................ ......................115 12.2.1 memory architecture and configuration.................................................................................... 115 12.2.1.1 connection memory ..................................................................................................115 12.2.1.2 data memory ............................................................................................................ .116 12.2.2 standard switching ....................................................................................................... ............117 12.2.2.1 constant delay and minimum delay connections ....................................................117 12.2.2.2 pattern mode ........................................................................................................... ..117 12.2.2.3 subrate ................................................................................................................ ......117 13 electrical characteristics................................................................................................... ..............................124 13.1 absolute maximum ratings ................................................................................................... ...............124 13.1.1 handling precautions ..................................................................................................... ...........124 13.2 crystal specifications ..................................................................................................... ......................124 13.2.1 xtal1 crystal ............................................................................................................ ...............124 13.2.2 xtal2 crystal ............................................................................................................ ...............125 13.2.3 reset pulse.............................................................................................................. .................126 13.3 thermal parameters (definitions and values)................................................................................ ......126 13.4 reliability ................................................................................................................ ..............................127 13.5 dc electrical characteristics.............................................................................................. ....................128 13.5.1 electrical drive specifications, ct_c8 and /ct_frame .........................................................128 13.5.2 all other pins ........................................................................................................... .................129 13.6 h-bus timing ............................................................................................................... .........................129 13.6.1 timing diagrams .......................................................................................................... .............129 13.7 ac electrical characteristics.............................................................................................. ....................130 13.7.1 skew timing, h-bus....................................................................................................... ...........130 13.8 hot swap ................................................................................................................... ...........................131 13.8.1 lpue (local pull-up enable).............................................................................................. ......131 13.9 decoupling................................................................................................................. ...........................131 13.10 apll v dd filter ........................................................................................................................ ............132 13.11 pc board pbga considerations .............................................................................................. ............133 13.12 unused pins ............................................................................................................... ..........................133 13.13 external pull-up pins..................................................................................................... .......................133 13.14 t8110l evaluation kits.................................................................................................... .....................133 13.15 t8110l ordering information............................................................................................... .................133 14 jtag/boundary scan ........................................................................................................... ..........................137 14.1 the principle of boundary-scan architecture................................................................................ .......137 14.1.1 instruction register ..................................................................................................... ..............138 14.2 boundary-scan register..................................................................................................... ..................138 a constant and minimum delay connections ........................................................................................ ............139 a.1 connection definitions...................................................................................................... ....................139 a.2 delay type definitions...................................................................................................... ....................139 b register bit field mnemonic summary........................................................................................... ................142 significant changes between the june 2003 and november 2003 release ........................................................163
list of figures figure page 6 agere systems inc. ambassador t8110l h.100/h.110 switch february 2004 data sheet figure 1. t8110l pull-up/pull-down arrangement for h1x0 pins .................................................................... ... 20 figure 2. t8110l architecture block diagram ..................................................................................... ................ 21 figure 3. microprocessor access timing, intel protocol ...................................................................................... 26 figure 4. microprocessor access timing, motorola protocol ............................................................................... 27 figure 5. t8110l main clocking paths ............................................................................................ .................... 44 figure 6. t8110l netref paths ................................................................................................... ..................... 44 figure 7. t8110l required frame pulse and bit clock with polarities ............................................................. .. 60 figure 8. t8110l phase alignment, snap and slide ................................................................................ ....... 62 figure 9. fallback?fixed vs. rotating secondary ................................................................................. ............. 65 figure 10. t8110l clock fallback states ......................................................................................... ..................... 66 figure 11. t8110l h-bus clock enable states ..................................................................................... ................ 68 figure 12. t8110l clock failsafe states ......................................................................................... ...................... 70 figure 13. fg[7:0] functional paths ............................................................................................. ......................... 77 figure 14. frame group 8 khz reference timing ................................................................................... .............. 78 figure 15. gp[7:0] functional paths ............................................................................................. ......................... 82 figure 16. local stream 16.384 mbits/s timing................................................................................... .................. 86 figure 17. local stream 16.384 mbits/s circuit .................................................................................. ................... 87 figure 18. superrate i/o configuration .......................................................................................... ........................ 88 figure 19. relationship between 8.192 mbits/s and 16.384 mbits/s time slots ................................................... 89 figure 20. interrupt controller ................................................................................................. ............................. 103 figure 21. microprocessor programming?reset page command ..................................................................... 114 figure 22. microprocessor programming?make/break/query telephony connections..................................... 114 figure 23. t8110l data memory map and configurations ............................................................................ ...... 116 figure 24. tdm data stream bit rates ............................................................................................ ................... 118 figure 25. subrate switching example, byte packing .............................................................................. ........... 121 figure 26. subrate switching example, byte unpacking ............................................................................ ......... 123 figure 27. clock alignment ...................................................................................................... ............................ 129 figure 28. frame timing diagram ................................................................................................. ...................... 130 figure 29. detailed clock skew timing diagram................................................................................... .............. 130 figure 30. apll v dd filtering ..................................................................................................................... ......... 132 figure 31. t8110l pins by functional group ...................................................................................... ................ 134 figure 32. ieee ? 1149.1 boundary-scan architecture ........................................................................................ 137 figure 33. constant delay connection latency.................................................................................... ............... 140 figure 34. minimum delay connection latency ..................................................................................... ............. 141
list of tables table page agere systems inc. 7 february 2004 ambassador t8110l h.100/h.110 switch data sheet table 1. microprocessor interface signals ....................................................................................... ...................10 table 2. h-bus (h.100/h.110 interface) signals .................................................................................. ...............10 table 3. l-bus (local) interface signals ........................................................................................ .....................10 table 4. clock circuit interface signals ........................................................................................ ......................11 table 5. gpio interface signals................................................................................................. .........................11 table 6. miscellaneous interface signals ........................................................................................ ....................11 table 7. jtag signals ........................................................................................................... .............................11 table 8. t8110l pinouts ......................................................................................................... ............................13 table 9. intel / motorola protocol selector ............................................................................................................2 2 table 10. t8110l memory mapping to microprocessor space......................................................................... ....23 table 11. microprocessor interface register map ................................................................................. ...............24 table 12. register space access timing .......................................................................................... ...................28 table 13. connection memory space access timing................................................................................. ..........28 table 14. data memory space access timing ....................................................................................... ..............29 table 15. control register map .................................................................................................. ..........................30 table 16. reset registers ....................................................................................................... ..............................31 table 17. master output enable register ......................................................................................... ....................32 table 18. data memory mode select register ...................................................................................... ...............32 table 19. clock register access select register ................................................................................. ................33 table 20. phase alignment select register ....................................................................................... ...................33 table 21. fallback control register ............................................................................................. .........................34 table 22. fallback type select register......................................................................................... ......................35 table 23. fallback trigger registers ............................................................................................ ........................35 table 24. watchdog select, c8, netref registers ................................................................................. ...........36 table 25. watchdog en registers ................................................................................................. .......................37 table 26. failsafe control register ............................................................................................. ..........................38 table 27. error and status register map ......................................................................................... .....................39 table 28. clock error registers ................................................................................................. ...........................40 table 29. latched clock error registers ......................................................................................... .....................41 table 30. fallback and failsafe status register ................................................................................. ..................42 table 31. system errors registers ............................................................................................... ........................43 table 32. device identification registers ....................................................................................... .......................43 table 33. clock input control register map ...................................................................................... ...................45 table 34. main input selector register .......................................................................................... .......................45 table 35. main divider register ................................................................................................. ...........................46 table 36. apll1 input selector register ......................................................................................... .....................46 table 37. apll1 rate register................................................................................................... ..........................47 table 38. main inversion select register........................................................................................ ......................47 table 39. resource divider register ............................................................................................. .......................48 table 40. apll2 rate register................................................................................................... ..........................48 table 41. lref input/inversion select registers ................................................................................. ................49 table 42. dpll1 input selector registers ........................................................................................ ....................50 table 43. dpll2 register ........................................................................................................ .............................51 table 44. netref1 registers ..................................................................................................... .........................51 table 45. netref2 registers ..................................................................................................... .........................52 table 46. clock output control register map..................................................................................... ..................53 table 47. master output enables registers ....................................................................................... ..................54 table 48. clock output format registers ......................................................................................... ....................55 table 49. tclk select and l_scx select registers ................................................................................ ............56 table 50. bit clock and frame ................................................................................................... ...........................57
list of tables (continued) table page 8 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch table 51. watchdog timer description ............................................................................................ .....................58 table 52. frame center sampling ................................................................................................. .......................59 table 53. legacy mode fallback event triggers ................................................................................... ...............65 table 54. clock fallback state description...................................................................................... .....................67 table 55. h-bus clock enable state description.................................................................................. ................69 table 56. clock failsafe state descriptions..................................................................................... .....................71 table 57. frame group and fg i/o register map................................................................................... .............72 table 58. fgx lower and upper start registers ................................................................................... ...............72 table 59. fgx width registers ................................................................................................... ..........................73 table 60. fgx rate registers .................................................................................................... ...........................73 table 61. fg7 counter (low and high byte) registers ............................................................................. ...........74 table 62. fgio data register.................................................................................................... ...........................75 table 63. fgio read mask register ............................................................................................... .....................75 table 64. fgio r/w register ..................................................................................................... ..........................76 table 65. gpio register ......................................................................................................... ..............................80 table 66. gpio data register .................................................................................................... ..........................80 table 67. gpio read mask register............................................................................................... .....................81 table 68. gpio r/w register ..................................................................................................... ..........................81 table 69. gpio override register ................................................................................................ ........................82 table 70. t8110l serial stream groupings........................................................................................ ..................84 table 71. h-bus rate registers.................................................................................................. ..........................85 table 72. l-bus rate registers .................................................................................................. ..........................85 table 73. interrupt control register map ........................................................................................ ......................90 table 74. fgio interrupt pending registers...................................................................................... ...................90 table 75. fgio edge/level and polarity registers ................................................................................ ..............91 table 76. gpio interrupt pending register ....................................................................................... ...................92 table 77. gpio edge/level and gpio polarity registers ........................................................................... .........93 table 78. system error interrupt assignments .................................................................................... .................93 table 79. system interrupt pending high/low registers........................................................................... ...........94 table 80. system interrupt enable high/low registers............................................................................ ............95 table 81. clock error interrupt assignments ..................................................................................... ...................96 table 82. clock interrupt pending high/low registers............................................................................ .............97 table 83. clock interrupt enable high/low registers............................................................................. ..............98 table 84. arbitration control register .......................................................................................... .........................99 table 85. syserr output select registers........................................................................................ ...............100 table 86. interrupt in-service register ......................................................................................... ......................101 table 87. diagnostics control register map...................................................................................... .................106 table 88. fg testpoint enable registers ......................................................................................... ..................106 table 89. fg[7:0] internal testpoint assignments ................................................................................ ..............107 table 90. testpoint enable registers ............................................................................................ .....................108 table 91. gp[7:0] internal testpoint assignments................................................................................ ..............109 table 92. state counter modes registers ......................................................................................... .................110 table 93. miscellaneous diagnostics low register ................................................................................ ............110 table 94. miscellaneous diagnostic registers.................................................................................... ................111 table 95. microprocessor programming, connection memory access ..............................................................113 table 96. tdm data stream ....................................................................................................... ........................118 table 97. subrate switching, data propagation rate vs. channel capacity ......................................................119 table 98. subrate switching, connection memory programming setup ............................................................120 table 99. absolute maximum ratings.............................................................................................. ...................124 table 100. xtal1 specifications ................................................................................................. .........................124
list of tables (continued) table page agere systems inc. 9 february 2004 ambassador t8110l h.100/h.110 switch data sheet table 101. 16.384 mhz oscillator requirements................................................................................... ...............125 table 102. xtal2 specifications ................................................................................................. .........................125 table 103. 6.176 mhz/12.352 mhz oscillator requirements ......................................................................... ......125 table 104. reset pulse .......................................................................................................... ...............................126 table 105. thermal parameter values............................................................................................. .....................127 table 106. reliability data..................................................................................................... ................................127 table 107. electrical drive specifications, ct_c8 and /ct_frame................................................................. ...128 table 108. dc electrical characteristics, all other pins ........................................................................ ................129 table 109. skew timing, h-bus ................................................................................................... .........................130 table 110. l_sc[3:0] and frame group rise and fall time ......................................................................... .......131 table 111. t8110l ordering information .......................................................................................... ....................133 table 112. instruction register................................................................................................. .............................138 table 113. special cases (exceptions)........................................................................................... ......................141 table 114. mnemonic summary, sorted by name..................................................................................... ...........143 table 115. mnemonic summary, sorted by register................................................................................. ...........153 table 116. changes .............................................................................................................. ................................163
10 10 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description 2.1 interface signals table 1. microprocessor interface signals signal i/o width microprocessor interface function a i 20 address[19:0] in. d i/o 16 data bus in/out. rd# (ds#) i 1 rdn(dsn) in. wr# (r/w#) i 1 wrn(r/wn) in. csn i 1 csn in. wb_sel i 1 word/byte select in. rdy (dtack#) out 1 rdy(dtackn) out. im_sel i 1 intel/motorola select in. table 2. h-bus (h.100/h.110 interface) signals signal i/o width function vprecharge in 1 precharge voltage for pull-downs, h.110 bus signals: ct_d, ct_netref1, ct_netref2. h110_enable in 1 pull-down enable for h.110 bus signals: ct_d, ct_netref1, ct_netref2. h100_enable in 1 pull-up enable for h.100 bus signals: ct_d, ct_netref1, ct_netref2, ct_c8_a, ct_c8_b, /ct_frame_a, /ct_frame_b. ct_d i/o 32 h.100/h.110 bus data. ct_c8_a i/o 1 h.100/h.110 bit clock a. /ct_frame_a i/o 1 h.100/h.110 frame reference a. ct_c8_b i/o 1 h.100/h.110 bit clock b. /ct_frame_b i/o 1 h.100/h.110 frame reference b. ct_netref1 i/o 1 h.100/h.110 network reference 1. ct_netref2 i/o 1 h.100/h.110 network reference 2. /c16+ i/o 1 h- mvip ? compatibility clock (16.384 mhz, differential). /c16? i/o 1 h- mvip compatibility clock (16.384 mhz, differential). /c4 i/o 1 mvip compatibility clock (4.096 mhz). c2 i/o 1 mvip compatibility clock (2.048 mhz). sclk i/o 1 sc-bus compatibility clock. /sclkx2 i/o 1 sc-bus compatibility clock. /fr_comp i/o 1 compatibility frame reference. table 3. l-bus (local) interface signals signal i/o width function l_d i/o 32 local bus data. l_sc out 4 local bus clock outputs. fg i/o 8 local frame groups.
agere systems inc. 11 data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.1 interface signals (continued) table 4. clock circuit interface signals signal i/o width function xtal1_in in 1 crystal oscillator #1 input (16.384 mhz). xtal1_out out 1 crystal oscillator #1 feedback. xtal2_in in 1 crystal oscillator #2 input (6.176 mhz or 12.352 mhz). xtal2_out out 1 crystal oscillator #2 feedback. lref in 8 local clock reference inputs. tclk_out out 1 internal chip clock output. pri_ref_out out 1 main divider reference out for clad/djat. pri_ref_in in 1 clad/djat reference in for apll1. nr1_sel_out out 1 ct_netref1 selection out for clad/djat. nr1_div_in in 1 clad/djat reference in for ct_netref1 divider. nr2_sel_out out 1 ct_netref2 selection out for clad/djat. nr2_div_in in 1 clad/djat reference in for ct_netref2 divider. table 5. gpio interface signals signal i/o width gpio function alternate function gp0 i/o 1 gpio bit 0 i/o a-master indicator out. gp1 i/o 1 gpio bit 1 i/o b-master indicator out. gp2 i/o 1 gpio bit 2 i/o ? gp3 i/o 1 gpio bit 3 i/o ? gp4 i/o 1 gpio bit 4 i/o ? gp5 i/o 1 gpio bit 5 i/o ? gp6 i/o 1 gpio bit 6 i/o ? gp7 i/o 1 gpio bit 7 i/o ? table 6. miscellaneous interface signals signal i/o width function reset# in 1 chip reset. syserr out 1 system error indicator. clkerr out 1 clocking error indicator. lpue in 1 pull-up enable for signals: fg, gp, l_d, lref, d, nr1_div_in, nr2_div_in, pri_ref_in. pen in 1 reserved. must be left unconnected. testmode in 1 reserved. must be left unconnected. table 7. jtag signals signal i/o width function trst# in 1 jtag reset. tck in 1 jtag clock. tms in 1 jtag mode select. tdi in 1 jtag data in. tdo out 1 jtag data out.
12 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.2 t8110l pinout information the t8110l package is a 272-pin pbga ball grid array. refer to the table below for ball assignment, buffer type, and pull-up/pull-down information. note: the pull-up/down column in the following table is defined as follows: ! 20 k ? down?20 k ? pull-down resistor is always in-circuit. ! 50 k ? up?50 k ? pull-up resistor is always in-circuit. ! lpue: 50 k ? up?when lpue = 1, a 50 k ? pull-up resistor is in-circuit. ! enabled: 50 k ? up/20 k ? vpre?when h100_enable = 1, a 50 k ? pull-up resistor is in-circuit (see figure 1 on page 20). when h110_enable = 1, a 20 k ? pull-down resistor from the vprecharge input to this signal is in- circuit.
agere systems inc. 13 data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.2 t8110l pinout information (continued) table 8. t8110l pinouts microprocessor interface ball pin name buffer type pull-up/down (see note on page 12) f1 a0 8 ma i/o-schmitt 20 k ? down g1 a1 8 ma i/o-schmitt 20 k ? down k3 a10 8 ma i/o-schmitt 20 k ? down j3 a11 8 ma i/o-schmitt 20 k ? down k1 a12 8 ma i/o-schmitt 20 k ? down k2 a13 8 ma i/o-schmitt 20 k ? down l3 a14 8 ma i/o-schmitt 20 k ? down l4 a15 8 ma i/o-schmitt 20 k ? down g2 a2 8 ma i/o-schmitt 20 k ? down g3 a3 8 ma i/o-schmitt 20 k ? down h1 a4 8 ma i/o-schmitt 20 k ? down h2 a5 8 ma i/o-schmitt 20 k ? down h3 a6 8 ma i/o-schmitt 20 k ? down j4 a7 8 ma i/o-schmitt 20 k ? down j1 a8 8 ma i/o-schmitt 20 k ? down j2 a9 8 ma i/o-schmitt 20 k ? down w1 d0 8 ma i/o-schmitt lpue: 50 k ? up v1 d1 8 ma i/o-schmitt lpue: 50 k ? up v2 d2 8 ma i/o-schmitt lpue: 50 k ? up u3 d3 8 ma i/o-schmitt lpue: 50 k ? up u1 d4 8 ma i/o-schmitt lpue: 50 k ? up u2 d5 8 ma i/o-schmitt lpue: 50 k ? up t3 d6 8 ma i/o-schmitt lpue: 50 k ? up t4 d7 8 ma i/o-schmitt lpue: 50 k ? up t1 d8 8 ma i/o-schmitt lpue: 50 k ? up t2 d9 8 ma i/o-schmitt lpue: 50 k ? up r3 d10 8 ma i/o-schmitt lpue: 50 k ? up p4 d11 8 ma i/o-schmitt lpue: 50 k ? up r1 d12 8 ma i/o-schmitt lpue: 50 k ? up r2 d13 8 ma i/o-schmitt lpue: 50 k ? up p2 d14 8 ma i/o-schmitt lpue: 50 k ? up p3 d15 8 ma i/o-schmitt lpue: 50 k ? up n1 rd#(ds#) 8 ma i/o-schmitt lpue: 50 k ? up p1 wr#(r/w#) 8 ma i/o-schmitt lpue: 50 k ? up l1 a16 8 ma i/o-schmitt 20 k ? down l2 a17 8 ma i/o-schmitt 20 k ? down m1 a18 8 ma i/o-schmitt 20 k ? down m2 a19 8 ma i/o-schmitt 20 k ? down m3 csn 8 ma i/o-schmitt lpue: 50 k ? up m4 wb_sel 8 ma i/o-schmitt lpue: 50 k ? up n2 rdy(dtack#) 8 ma 3-state external pull-up required n3 im_sel 8 ma i/o-schmitt lpue: 50 k ? up
14 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.2 t8110l pinout information (continued) table 8. t8110l pinouts (continued) h-bus interface ball pin name buffer type pull-up/down (see note on page 12) c1 vprecharge op amp noninvert ? d5 h110_enable input 20 k ? down d7 h100_enable input 20 k ? down a11 ct_d0 pci i/o enabled: 50 k ? up/20 k ? vpre b11 ct_d1 pci i/o enabled: 50 k ? up/20 k ? vpre c10 ct_d2 pci i/o enabled: 50 k ? up/20 k ? vpre c11 ct_d3 pci i/o enabled: 50 k ? up/20 k ? vpre a10 ct_d4 pci i/o enabled: 50 k ? up/20 k ? vpre b10 ct_d5 pci i/o enabled: 50 k ? up/20 k ? vpre b9 ct_d6 pci i/o enabled: 50 k ? up/20 k ? vpre c9 ct_d7 pci i/o enabled: 50 k ? up/20 k ? vpre a9 ct_d8 pci i/o enabled: 50 k ? up/20 k ? vpre b8 ct_d9 pci i/o enabled: 50 k ? up/20 k ? vpre c8 ct_d10 pci i/o enabled: 50 k ? up/20 k ? vpre a8 ct_d11 pci i/o enabled: 50 k ? up/20 k ? vpre c7 ct_d12 pci i/o enabled: 50 k ? up/20 k ? vpre a7 ct_d13 pci i/o enabled: 50 k ? up/20 k ? vpre b7 ct_d14 pci i/o enabled: 50 k ? up/20 k ? vpre c6 ct_d15 pci i/o enabled: 50 k ? up/20 k ? vpre a6 ct_d16 pci i/o enabled: 50 k ? up/20 k ? vpre b6 ct_d17 pci i/o enabled: 50 k ? up/20 k ? vpre c5 ct_d18 pci i/o enabled: 50 k ? up/20 k ? vpre a5 ct_d19 pci i/o enabled: 50 k ? up/20 k ? vpre b5 ct_d20 pci i/o enabled: 50 k ? up/20 k ? vpre a4 ct_d21 pci i/o enabled: 50 k ? up/20 k ? vpre b4 ct_d22 pci i/o enabled: 50 k ? up/20 k ? vpre c4 ct_d23 pci i/o enabled: 50 k ? up/20 k ? vpre a3 ct_d24 pci i/o enabled: 50 k ? up/20 k ? vpre b3 ct_d25 pci i/o enabled: 50 k ? up/20 k ? vpre c3 ct_d26 pci i/o enabled: 50 k ? up/20 k ? vpre a2 ct_d27 pci i/o enabled: 50 k ? up/20 k ? vpre b2 ct_d28 pci i/o enabled: 50 k ? up/20 k ? vpre b1 ct_d29 pci i/o enabled: 50 k ? up/20 k ? vpre c2 ct_d30 pci i/o enabled: 50 k ? up/20 k ? vpre d2 ct_d31 pci i/o enabled: 50 k ? up/20 k ? vpre a13 ct_c8_a 24 ma i/o-schmitt enabled: 50 k ? up a12 /ct_frame_a 24 ma i/o-schmitt enabled: 50 k ? up b13 ct_c8_b 24 ma i/o-schmitt enabled: 50 k ? up b12 /ct_frame_b 24 ma i/o-schmitt enabled: 50 k ? up a14 ct_netref1 pci i/o enabled: 50 k ? up/20 k ? vpre b14 ct_netref2 pci i/o enabled: 50 k ? up/20 k ? vpre d9 /c16+ 24 ma i/o-schmitt 50 k ? up
agere systems inc. 15 data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.2 t8110l pinout information (continued) table 8. t8110l pinouts (continued) h-bus interface (continued) ball pin name buffer type pull-up/down (see note on page 12) d10 /c16? 24 ma i/o-schmitt 50 k ? up d12 /c4 8 ma i/o-schmitt 50 k ? up d14 c2 8 ma i/o-schmitt 50 k ? up c14 sclk 24 ma i/o-schmitt 50 k ? up c13 /sclkx2 24 ma i/o-schmitt 50 k ? up c12 /fr_comp 24 ma i/o-schmitt 50 k ? up j20 ld0 8 ma i/o-schmitt lpue: 50 k ? up j19 ld1 8 ma i/o-schmitt lpue: 50 k ? up j18 ld2 8 ma i/o-schmitt lpue: 50 k ? up k17 ld3 8 ma i/o-schmitt lpue: 50 k ? up k20 ld4 8 ma i/o-schmitt lpue: 50 k ? up k19 ld5 8 ma i/o-schmitt lpue: 50 k ? up k18 ld6 8 ma i/o-schmitt lpue: 50 k ? up l18 ld7 8 ma i/o-schmitt lpue: 50 k ? up l20 ld8 8 ma i/o-schmitt lpue: 50 k ? up l19 ld9 8 ma i/o-schmitt lpue: 50 k ? up m18 ld10 8 ma i/o-schmitt lpue: 50 k ? up m17 ld11 8 ma i/o-schmitt lpue: 50 k ? up m20 ld12 8 ma i/o-schmitt lpue: 50 k ? up m19 ld13 8 ma i/o-schmitt lpue: 50 k ? up n19 ld14 8 ma i/o-schmitt lpue: 50 k ? up n18 ld15 8 ma i/o-schmitt lpue: 50 k ? up n20 ld16 8 ma i/o-schmitt lpue: 50 k ? up p20 ld17 8 ma i/o-schmitt lpue: 50 k ? up p19 ld18 8 ma i/o-schmitt lpue: 50 k ? up p18 ld19 8 ma i/o-schmitt lpue: 50 k ? up r20 ld20 8 ma i/o-schmitt lpue: 50 k ? up r19 ld21 8 ma i/o-schmitt lpue: 50 k ? up r18 ld22 8 ma i/o-schmitt lpue: 50 k ? up p17 ld23 8 ma i/o-schmitt lpue: 50 k ? up t20 ld24 8 ma i/o-schmitt lpue: 50 k ? up t19 ld25 8 ma i/o-schmitt lpue: 50 k ? up t18 ld26 8 ma i/o-schmitt lpue: 50 k ? up u20 ld27 8 ma i/o-schmitt lpue: 50 k ? up v20 ld28 8 ma i/o-schmitt lpue: 50 k ? up u19 ld29 8 ma i/o-schmitt lpue: 50 k ? up u18 ld30 8 ma i/o-schmitt lpue: 50 k ? up t17 ld31 8 ma i/o-schmitt lpue: 50 k ? up h20 l_sc0 8 ma 3-state ? h19 l_sc1 8 ma 3-state ? h18 l_sc2 8 ma 3-state ? g19 l_sc3 8 ma 3-state ?
16 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.2 t8110l pinout information (continued) table 8. t8110l pinouts (continued) l-bus interface ball pin name buffer type pull up/down (see note on page 12) y20 fg0 8 ma i/o-schmitt lpue: 50 k ? up y19 fg1 8 ma i/o-schmitt lpue: 50 k ? up w20 fg2 8 ma i/o-schmitt lpue: 50 k ? up w19 fg3 8 ma i/o-schmitt lpue: 50 k ? up w18 fg4 8 ma i/o-schmitt lpue: 50 k ? up v19 fg5 8 ma i/o-schmitt lpue: 50 k ? up v18 fg6 8 ma i/o-schmitt lpue: 50 k ? up v17 fg7 8 ma i/o-schmitt lpue: 50 k ? up b20 xtal1_in input ? c19 xtal1_out crystal feedback ? e20 xtal2_in input ? f19 xtal2_out crystal feedback ? a15 lref0 input-schmitt lpue: 50 k ? up b15 lref1 input-schmitt lpue: 50 k ? up c15 lref2 input-schmitt lpue: 50 k ? up c16 lref3 input-schmitt lpue: 50 k ? up a16 lref4 input-schmitt lpue: 50 k ? up b16 lref5 input-schmitt lpue: 50 k ? up clock circuit interface ball pin name buffer type pull up/down (see note on page 12) b17 lref6 input-schmitt lpue: 50 k ? up c17 lref7 input-schmitt lpue: 50 k ? up g20 tclk_out 8 ma 3-state ? a17 pri_ref_out 8 ma 3-state ? a18 pri_ref_in input-schmitt lpue: 50 k ? up b18 nr1_sel_out 8 ma 3-state ? a19 nr1_div_in input-schmitt lpue: 50 k ? up d19 nr2_sel_out 8 ma 3-state ? c20 nr2_div_in input-schmitt lpue: 50 k ? up gpio interface ball pin name buffer type pull up/down (see note on page 12) d1 gp0/amaster 8 ma i/o-schmitt lpue: 50 k ? up e1 gp1/bmaster 8 ma i/o-schmitt lpue: 50 k ? up e2 gp2 8 ma i/o-schmitt lpue: 50 k ? up f2 gp3 8 ma i/o-schmitt lpue: 50 k ? up d3 gp4 8 ma i/o-schmitt lpue: 50 k ? up f3 gp5 8 ma i/o-schmitt lpue: 50 k ? up e3 gp6 8 ma i/o-schmitt lpue: 50 k ? up e4 gp7 8 ma i/o-schmitt lpue: 50 k ? up
agere systems inc. 17 data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.2 t8110l pinout information (continued) table 8. t8110l pinouts (continued) miscellaneous interfaces ball pin name buffer type pull up/down (see note on page 12) y1 reset# input-schmitt 50 k ? up v3 syserr 8 ma 3-state ? w2 clkerr 8 ma 3-state ? j17 lpue input 50 k ? up a20 pen input 50 k ? up. this pin is unused and must be left unconnected. f20 testmode input 20 k ? up. this pin is unused and must be left unconnected. jtag interface ball pin name buffer type pull up/down (see note on page 12) c18 trst# input-schmitt 50 k ? up e18 tck input-schmitt 50 k ? up d18 tms input-schmitt 50 k ? up f18 tdi input-schmitt 50 k ? up g18 tdo 4 ma 3-state ? power ball pin name buffer type pull up/down b19 apll1v dd analog v dd ? e19 apll2v dd analog v dd ? d6 v dd ?? d11 v dd ?? d15 v dd ?? f4 v dd ?? f17 v dd ?? k4 v dd ?? l17 v dd ?? r4 v dd ?? r17 v dd ?? u6 v dd ?? u10 v dd ?? u15 v dd ?? ground ball pin name buffer type pull up/down a1 v ss ?? d4 v ss ?? d8 v ss ?? d13 v ss ?? d17 v ss ?? h4 v ss ?? h17 v ss ??
18 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.2 t8110l pinout information (continued) table 8. t8110l pinouts (continued) ground (continued) ball pin name buffer type pull up/down n4 v ss ?? n17 v ss ?? u4 v ss ?? u8 v ss ?? u13 v ss ?? u17 v ss ?? u5 v ss ?? u11 v ss ?? u16 v ss ?? w5?w9 v ss ?? w10 v ss ?? w13?w17 v ss ?? v4?v9 v ss ?? v13?v16 v ss ?? y5?y9 v ss ?? y13?y18 v ss ?? thermal ground j9?12 ? ? ? k9?12 ? ? ? l9?12 ? ? ? m9?12 ? ? ? no connects d16 no connects must be left unconnected. d20 e17 g17 g4 w3 v12 y4
agere systems inc. 19 data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.2 t8110l pinout information (continued) note: the epu pins must be tied to an exernal pull-up resistor. multiple pins may share a common resistor. it is recommended tha t all epu pins be tied to a common 20 k ? pull-up resistor. table 8. t8110l pinouts (continued) external pull-up ball pin name buffer type pull up/down u7 epu ? ? u9 epu ? ? u12 epu ? ? u14 epu ? ? v10 epu ? ? v11 epu ? ? w4 epu ? ? w11 epu ? ? w12 epu ? ? y2 epu ? ? y3 epu ? ? y10 epu ? ? y11 epu ? ? y12 epu ? ?
20 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 2 pin description (continued) 2.3 special buffer requirements 2.3.1 h1x0 bus signal internal pull-up/pull-down the h1x0 bus pins require special consideration for h.100 and h.110 usage. there are two control pins to select between various internal bus pull-ups/pull-downs, as shown below: ! h100_enable. enables internal 50 k ? pull-ups on ct_dn, ct_netref1, ct_netref2, ct_c8_a, ct_c8_b, /ct_frame_a, and /ct_frame_b signals. ! h110_enable. enables internal 20 k ? pull-downs on all 32 ct_dn signals, ct_netref1, and ct_netref2 to the vprecharge signal. note: the two h1x0 enables are active-high. only one or the other should ever be asserted. warning: do not assert both at the same time. please refer to figure 1 for more detail. 5-9611 (f) figure 1. t8110l pull-up/pull-down arrangement for h1x0 pins 2.3.2 local bus signal internal pull-up the lpue input is active-high; and is used to activate pull-ups on the following local signals: gp[7:0], fg[7:0], d[15:0], ld[31:0], lref[7:0], pri_ref_in, nr1_div_in, and nr2_div_in. pad pad pad pad 50 k ? , min pad 20 k ? , min v dd v dd 50 k ? , min ct_c8_a, ct_c8_b, /ct_frame_a, /ct_frame_b to other ct_dn vprecharge h100_enable h110_enable ct_dn, ct_netref1, ct_netref2 apply 0.7 v, nominal
agere systems inc. 21 data sheet february 2004 ambassador t8110l h.100/h.110 switch 3 main architectural features 3.1 t8110l architecture the t8110l includes all of the clocking and standard switching functions found on previous ambassador devices, plus additional functionalities that are described in the following sections. the t8110l interfaces to a controller via a standard microprocessor interface which is described in section 4. note that the full version of the device, the t8110, contains both microprocessor and pci interfaces, allowing the device to attach directly to a pci bus. the t8110l and t8110 are pin compatible. figure 2. t8110l architecture block diagram error signals general- purpose i/o frame groups additional i/o interrupt and error control general- purpose i/o clocking and timing control h1x0 even connection memory h1x0 odd connection memory local high connection memory local low connection memory connection memory controller register access control microprocessor interface system errors internal clocks local clocks h1x0 clocks errors clock fg timing data memory controller data memory 2k x 8 data memory 2k x 8 parallel-to-serial conversion (output) serial-to-parallel conversion (input) h1x0 streams (bidirectional) local streams (bidirectional) frame groups and gp i/o address data 5-8920 (f)
22 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 4 microprocessor interface 4.1 intel/motorola protocol selector im_sel = 1 is the default, if left unconnected, and selects an intel handshake protocol. im_sel = 0 selects a motorola handshake protocol. note: the im_sel signal must be static (either pulled high or pulled low). 4.2 word/byte addressing selector wb_sel = 1 is the default, if left unconnected, and selects 16-bit word aligned addressing. wb_sel = 0 selects 8-bit byte aligned addressing. note: the wb_sel signal may be static or dynamic in nature. if dynamic, wb_sel must follow the same timing requirements as the address bus. word-aligned addressing produces 16-bit data transfers via d[15:0]. byte-aligned addressing produces 8-bit data transfers via d[7:0] (d[15:8] is unused). the t8110l internal data bus is 32 bits, so a[1:0] address bits are decoded along with wb_sel to control a dword-to-word or dword-to-byte swap function back to the data bus. table 9. intel/motorola protocol selector intel/motorola protocol selector signal intel mnemonic motorola mnemonic d[15:0] d[15:0] d[15:0] a[19:0] a[15:0] a[15:0] csn csn csn rdy (dtack#) rdy dtackn rd# (ds#) rdn (read strobe) dsn (data strobe) wr# (r/w#) wrn (write strobe) r/wn (read/write selector) wb_sel default default im_sel default default
agere systems inc. 23 data sheet february 2004 ambassador t8110l h.100/h.110 switch 4 microprocessor interface (continued) 4.3 access via the microprocessor bus the t8110l microprocessor bus interface allows access to three internal regions: registers, connection memory, and data memory. all microprocessor bus asynchronous strobes are synchronized to the t8110l's internal 65.536 mhz clock domain. there are 20 address bits provided to address the internal regions and these are defined in table 10. table 10. t8110l memory mapping to microprocessor space region subregion range (hex) registers reserved 0x00000?0x000ff operating control and status 0x00100?0x001ff clocks 0x00200?0x002ff rate control 0x00300?0x003ff frame group 0x00400?0x004ff general-purpose i/o 0x00500?0x005ff interrupt control 0x00600?0x006ff reserved 0x00700?0x007ff reserved 0x00800?0x0ffff reserved ? 0x10000?0x1ffff data memory ? 0x20000?0x2ffff reserved ? 0x30000?0x3ffff connection memory ? 0x40000?0x4ffff reserved ? 0x50000?0xfffff
24 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 4 microprocessor interface (continued) 4.3 access via the microprocessor bus (continued) 4.3.1 microprocessor interface register map the t8110l registers map into the microprocessor bus space as follows. table 11. microprocessor interface register map dword address (20 bits) cross reference register byte 3 byte 2 byte 1 byte 0 0x00100 5.1.1, 5.1.2 master enable reserved reset select soft reset 0x00104 5.1.3, 5.1.4 phase alignment select clock register access select data memory mode select reserved 0x00108 5.1.4 fallback trigger, upper fallback trigger, lower fallback type select fallback control 0x0010c 5.1.4 watchdog en, upper watchdog en, lower watchdog select, netref watchdog select, c8 0x00114 4.1.5 reserved failsafe sensitivity failsafe enable failsafe control 0x00118 6.1.11 reserved ool monitor ool threshold high ool threshold low 0x00120 5.2.1 status 3, latched clock errors, upper status 2, latched clock errors, lower status 1, transient clock errors, upper status 0, transient clock errors, lower 0x00124 5.2.2 status 7, system errors reserved reserved status 4 0x00128 5.2.2.2 device id, upper device id, lower reserved version id 0x00140 11.1 diag3 diag2 diag1 diag0 0x00144 11.1 diag7 diag6 diag5 diag4 0x00148 11.1 diag11 diag10 diag9 diag8 0x00200 6.1 apll1 rate apll1 input selector main divider main input selector 0x00204 6.1 apll2 rate reserved resource divider main inversion select 0x00208 6.1 dpll1 rate dpll1 input selector reserved lref input select 0x0020c 6.1 dpll2 rate dpll2 input selector reserved lref inversion select 0x00210 6.1 reserved netref1 lref select netref1 divider netref1 input selector 0x00214 6.1 reserved netref2 lref select netref2 divider netref2 input selector 0x00220 6.2 c8 output rate /fr_comp width netref output enables master output enables 0x00224 6.2 sclk output rate tclk select reserved cclk output enables 0x00228 6.2 l_sc3 select l_sc2 select l_sc1 select l_sc0 select 0x00300 9.1 h-bus rate h/g h-bus rate f/e h-bus rate d/c h-bus rate b/a 0x00320 9.2 l-bus rate h/g l-bus rate f/e l-bus rate d/c l-bus rate b/a 0x00400 7.1 fg0 rate fg0 width fg0 upper start fg0 lower start
agere systems inc. 25 data sheet february 2004 ambassador t8110l h.100/h.110 switch 4 microprocessor interface (continued) 4.3 access via the microprocessor bus (continued) 4.3.1 microprocessor interface register map (continued) table 11. microprocessor interface register map (continued) dword address (20 bits) cross reference register byte 3 byte 2 byte 1 byte 0 0x00410 7.1 fg1 rate fg1 width fg1 upper start fg1 lower start 0x00420 7.1 fg2 rate fg2 width fg2 upper start fg2 lower start 0x00430 7.1 fg3 rate fg3 width fg3 upper start fg3 lower start 0x00440 7.1 fg4 rate fg4 width fg4 upper start fg4 lower start 0x00450 7.1 fg5 rate fg5 width fg5 upper start fg5 lower start 0x00460 7.1 fg6 rate fg6 width fg6 upper start fg6 lower start 0x00470 7.1 fg7 rate fg7 width fg7 upper start fg7 lower start 0x00474 7.2 fg7 mode upper fg7 mode lower fg7 counter high byte fg7 counter low byte 0x00480 7.3 reserved fgio r/w fgio read mask fgio data register 0x00500 8.1 gpio override gpio r/w gpio read mask gpio data register 0x00600 12.1 fgio interrupt polarity reserved fgio interrupt enable fgio interrupt pend- ing 0x00604 10.1 gpio interrupt polarity reserved gpio interrupt enable gpio interrupt pend- ing 0x00608 10.1 system interrupt enable, upper system interrupt enable, lower system interrupt pending, upper system interrupt pending, lower 0x0060c 10.1 clock interrupt enable, upper clock interrupt enable, lower clock interrupt pending, upper clock interrupt pend- ing, lower 0x00610 10.1 clkerr output select syserr output select reserved arbitration control 0x00614 10.1 clkerr pulse width syserr pulse width reserved reserved 0x006fc 10.1 reserved reserved in-service, high in-service, low
26 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 4 microprocessor interface (continued) 4.3 access via the microprocessor bus (continued) 4.3.1 microprocessor interface register map (continued) 5-9419 (f) figure 3. microprocessor access timing, intel protocol address valid tah trdyhi tas taccess word/byte select, a[19:0] csn wrn d[15:0], write cycle wr data valid tds tdh rdy trdylo microprocessor access write cycle, intel protocol address valid tah trdyhi tas taccess word/byte select, a[19:0] csn rdn rdy trdylo tdz read data valid d[15:0], tde tdv read cycle microprocessor access read cycle, intel protocol 5-9418 (f)
agere systems inc. 27 data sheet february 2004 ambassador t8110l h.100/h.110 switch 4 microprocessor interface (continued) 4.3 access via the microprocessor bus (continued) 4.3.1 microprocessor interface register map (continued) 5-9417 (f) figure 4. microprocessor access timing, motorola protocol address valid tah tdtackhi tdtacklo tde tdv tdz tas read data valid taccess word/byte select, a[19:0] r/wn csn dsn dtackn d[15:0], read cycle 5-9416 (f) microprocessor access read cycle, motorola protocol address valid tah tdtackhi tdtacklo tas taccess word/byte select, a[19:0] r/wn csn dsn dtackn d[15:0], write cycle wr data valid tds tdh microprocessor access write cycle, motorola protocol
28 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 4 microprocessor interface (continued) 4.3 access via the microprocessor bus (continued) 4.3.2 register space access the t8110l registers are always immediately available for access, providing low latency time to acknowledge the transaction. read access to [reserved] addresses returns 0x00. register access timing for figure 3 and figure 4 is shown below. 4.3.3 connection memory space access the t8110l connection memory is always immediately available for access (via dedicated access times assigned for microprocessor transactions) providing low latency time to acknowledge the transaction. connection memory access timing for figure 3 and figure 4 is shown below. table 12. register space access timing name parameter min (ns) max (ns) taccess overall access time 41 ? tas address setup time 5 ? tah address hold time 0 ? trdylo intel cycle, time to rdy deasserted 6 12 trdyhi intel cycle, time to rdy reasserted 36 72 tdtacklo motorola cycle, time to dtackn asserted 36 70 tdtackhi motorola cycle, time to dtackn deasserted 10 15 tde read cycle, time to data enabled 7 14 tdv read cycle, time to data valid 5 9 tdz read cycle, time to data invalid 10 16 tds write cycle, data setup time 25 ? tdh write cycle, data hold time 0 ? table 13. connection memory space access timing name parameter min (ns) max (ns) taccess overall access time 41 ? tas address setup time 5 ? tah address hold time 0 ? trdylo intel cycle, time to rdy deasserted 6 12 trdyhi intel cycle, time to rdy reasserted 36 72 tdtacklo motorola cycle, time to dtackn asserted 36 70 tdtackhi motorola cycle, time to dtackn deasserted 10 15 tde read cycle, time to data enabled 7 14 tdv read cycle, time to data valid 5 9 tdz read cycle, time to data invalid 10 16 tds write cycle, data setup time 25 ? tdh write cycle, data hold time 0 ?
agere systems inc. 29 data sheet february 2004 ambassador t8110l h.100/h.110 switch 4 microprocessor interface (continued) 4.3 access via the microprocessor bus (continued) 4.3.4 data memory space access the t8110l data memory is not guaranteed to be immediately available for access. access to data memory is pri- oritized for standard h-bus/l-bus switching, with microprocessor bus transaction access allowed as the lowest pri- ority. the latency time to acknowledge these transactions is indeterminate and depends on the h-bus/l-bus switching configuration. data memory access timing for figure 3 and figure 4 is shown below. * max data memory space access time is indeterminate, and depends on how much of the data memory access bandwidth is being taken by tdm switch connections. table 14. data memory space access timing name parameter min (ns) max (ns) taccess overall access time 41 ?* tas address setup time 5 ? tah address hold time 0 ? trdylo intel cycle, time to rdy deasserted 6 12 trdyhi intel cycle, time to rdy reasserted 36 ?* tdtacklo motorola cycle, time to dtackn asserted 36 ?* tdtackhi motorola cycle, time to dtackn deasserted 10 15 tde read cycle, time to data enabled 7 14 tdv read cycle, time to data valid 5 9 tdz read cycle, time to data invalid 10 16 tds write cycle, data setup time 25 ? tdh write cycle, data hold time 0 ?
30 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status overall t8110l operational control and status is configured via registers occupying 0x00100?0x001fc in the address space. 5.1 control registers general control functions are soft reset, reset configuration, overall master output enables, and data memory con- figuration. clocking-specific general control functions are clock register access configuration, phase alignment, clock fallback, and clock watchdog configuration. 5.1.1 reset registers the soft reset and reset select registers control soft reset functions and reset signal masking. writes to the soft reset register trigger the corresponding action, and the set bit(s) are automatically cleared. ! power-on reset : nonmaskable: ? at power-on, initialize all t8110l registers (including reset select register) and connection valid flags. the power-on reset cell test input is controlled via diagnostic register; see section 11. ! hard reset : maskable via reset select register, hrbeb: ? on assertion of reset#, initialize all t8110l registers (excluding reset select register) and connection valid flags. soft resets are maskable via reset select register, srbeb, and selectable via soft reset register, sresr. ! soft reset 1: initialize all t8110l registers (excluding reset select register) and connection valid flags. ! soft reset 2: initialize all t8110l registers (excluding reset select register). ! soft reset 3: reset all interrupt pending registers and the interrupt in-service register. ! soft reset 4: reset the interrupt in-service register only. table 15. control register map dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00100 master enable reserved reset select soft reset 0x00104 phase alignment select clock register access select data memory mode select ? 0x00108 fallback trigger, upper fallback trigger, lower fallback type select fallback control 0x0010c watchdog en, upper watchdog en, lower watchdog select, netref watchdog select, c8 0x00114 reserved failsafe threshold low failsafe enable and status failsafe control
agere systems inc. 31 data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.1 control registers (continued) 5.1.2 master output enable register the master output enable register is used to control master output enables to various groups of t8110l signals, including the following: l-bus data streams (l_d[31:0]) l-bus clocks (l_sc[3:0], fg[7:0] when used as frame group outputs) h-bus data streams (ct_d[31:0]) h-bus clocks (ct_c8_a, /ct_frame_a, ct_c8_b, /ct_frame_b, ct_netref1,ct_netref2, /c16+, /c16?, /c4, c2, sclk, /sclkx2, /fr_comp) gpio (gp[7:0]) fgio (fg[7:0] when used as programmable register outputs) t8110l outputs that are not programmatically enabled (i.e., always driven except during reset) include the follow- ing: clkerr, syserr, pri_ref_out, nr1_sel_out, and nr2_sel_out. table 16. reset registers byte address name bit(s) mnemonic value function 0x00100 soft reset 7:0 sresr 0000 0000 0000 0001 0000 0010 0001 0000 0010 0000 nop (default value). reset all registers and connection valid flags. reset all registers. reset interrupt pending and in-service registers. reset interrupt in-service register only. 0x00101 reset select 7:2 reserved 0000 nop (default). 1 hrbeb 0 1 disable hard reset to back end. enable hard reset to back end (default). 0srbeb 0 1 disable soft resets to back end. enable soft resets to back end (default).
32 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.1 control registers (continued) 5.1.3 connection control?data memory selector register the data memory mode select register msbit controls subrate switching enable. the lower 7 bits control the t8110l data memory switching configuration. for more details, see section 12.2.1.2 on page 116. there are three data memory configurations as outlined below: 1. 4k single-buffered switch. standard h-bus/l-bus switching only, up to 4096 simplex connections, all connections are minimum delay due to single-buffer configuration. 2. 2k double-buffered switch. standard h-bus/l-bus switching only, up to 2048 simplex connections, all connec- tions are programmable for minimum or constant delay via the double-buffer configuration. 3. 2k single-buffered switch + 1k double-buffered switch. standard h-bus/l-bus switching only, up to 2048 simplex minimum delay connections (single buffer) and up to 1024 simplex minimum or constant delay connections (double buffer). table 17. master output enable register byte address name bit(s) mnemonic value function 0x00103 master enable 7 aioeb 0 1 individual enables via bits [6:0] (default). enable all (same as bits [6:0] = 1111111). 6 reserved 0 nop. 5fgreb 0 1 disable fgio (default). enable fgio. 4gpieb 0 1 disable gpio (default). enable gpio. 3 hckeb 0 1 disable h-bus clocks (default). enable h-bus clocks. 2 hdbeb 0 1 disable h-bus data streams (default). enable h-bus data streams. 1lckeb 0 1 disable l-bus clocks, l_sc, fg (default). enable l-bus clocks. 0ldbeb 0 1 disable l-bus data streams (default). enable l-bus data streams. table 18. data memory mode select register byte address name bit(s) mnemonic value function 0x00105 data memory mode select 7gsreb 0 1 disable subrate switching (default). enable subrate switching. 6:0 dmmsp 100 0000 010 0000 011 0000 4k single-buffer switch (default). 2k double-buffer switch. 2k single-buffer, 1k double-buffer switch.
agere systems inc. 33 data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.1 control registers (continued) 5.1.4 general clock control (phase alignment, fallback, watchdogs) register the clock register access select register controls the selection between accessing the active vs. the inactive set of t8110l clock registers. the t8110l contains two sets of clock registers, x and y. the x and y register sets are comprised of the registers listed in table 33 on page 45, clock input control register map, and table 46 on page 53, clock output control register map. only one set is used at a time. it is selected based on the clock fallback setup. the clock register set that is currently in use is denoted as the active set; see section 6.3 on page 57 for more details. 5.1.5 phase alignment select register the phase alignment select register selects the phase alignment configuration. for more details, see section 6.4.5.1 on page 62. the t8110l internally generates an 8 khz frame reference. shown below are three configura- tions to control phase alignment between this internally generated frame reference and a selected incoming frame reference from the h-bus (/ct_frame_a, /ct_frame_b, or /fr_comp) or local clock reference (lref[4:7]). ! disable alignment, no realignment of unaligned frames ! snap alignment, immediate realignment of unaligned frames ! slide alignment, gradual realignment of unaligned frames 5.1.6 fallback control register the fallback control register allows user control over the active and inactive clock register sets. for more details, see section 6.7.1 on page 64. writes to the fallback control register trigger the corresponding action, and the set bit(s) are automatically cleared. the four commands are shown below: ! go_clocks. at initialization, the clock register y set is active, the x set is inactive, and access is enabled to the x set. the go_clocks command transitions the y set to inactive and the x set to active. this command can either be performed immediately upon issue or can wait to be performed until the next 8 khz frame refer- ence (synchronized to frame). ! clear_fallback. forces a state transition for active/inactive assignment of the clock register x and y sets after a fallback event has occurred. this command can either be performed immediately upon issue or can wait to be performed until the next 8 khz frame reference (synchronized to frame). table 19. clock register access select register byte address name bit(s) mnemonic value function 0x00106 clock register access select 7:0 csasr 0000 0000 0000 0001 access inactive clock registers (default). access active clock registers. table 20. phase alignment select register byte address name bit(s) mnemonic value function 0x00107 phase alignment select 7:0 pafsr 0000 0000 0000 0001 0000 0010 phase alignment is disabled (default). enable snap alignment. enable slide alignment.
34 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.1 control registers (continued) 5.1.6 fallback control register (continued) ! force_fallback. forces a state transition for active/inactive assignment of the clock register x and y sets by creating a fallback event. this command can either be performed immediately upon issue or can wait to be performed until the next 8 khz frame reference (synchronized to frame). ! copy active to inactive set. copies all register values in the current active clock register set to the inac- tive clock register set. this command is performed immediately upon issue. * the synchronized to frame command also has a diagnostic element?instead of performing the command right at the frame boundary, the user can elect to perform the command at a specified offset time from the frame boundary, by programming the diag11 and dia g10 registers, 0x0014b?0x0014a. 5.1.7 fallback type select register the upper nibble configures which h-bus clocks are selected to trigger a clock fallback event. any of the legacy modes have predetermined trigger enables and ignore the fallback trigger register settings. nonlegacy modes require the fallback trigger register settings. for more details, see section 6.7.1 on page 64. the lower nibble configures the state machine that controls clock register set active/inactive assignments. there are three possible selections. for more details, see section 6.7 on page 64. ! disabled. no transitions of clock register x and y sets to active/inactive. ! fixed secondary. swap the active/inactive sets on a fallback event; swap them back when fallback is cleared. ! rotating secondary. swap the active/inactive sets on a fallback event; maintain this state when fallback is cleared. table 21. fallback control register byte address name bit(s) mnemonic value function 0x00108 fallback control 7:0 fbcsr 0000 0000 0000 0001 0000 0010 0000 0100 0001 0001 0001 0010 0001 0100 0010 0000 nop (default). go_clocks command. clear_fallback command. force_fallback command. go_clocks synchronized to frame*. clear_fallback synchronized to frame*. force_fallback synchronized to frame*. copy active to inactive set com- mand.
agere systems inc. 35 data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.1 control registers (continued) 5.1.7 fallback type select register (continued) 5.1.8 fallback trigger registers the fallback trigger registers are used in conjunction with the fallback type select register and control which h-bus clocks are enabled to trigger a clock fallback event in case of error. the sync reference inputs to dpll1 and dpll2 can also trigger a clock fallback event upon detection of an error. table 22. fallback type select register byte address name bit(s) mnemonic value function 0x00109 fallback type select 7:4 ftrsn 0000 0001 0010 0100 1000 1001 nop (default). legacy, fallback to osc/4 on main select failure. legacy, fallback x/y set on main select failure. legacy, fallback x/y set on h-bus a/b failure. fallback trigger registers control fallback. fallback trigger registers control fallback and h-bus clock enable state machine is enabled. 3:0 fsmsn 0000 0001 0010 fallback is disabled (default). enable fixed secondary fallback. enable rotating secondary fallback. table 23. fallback trigger registers byte address name bit(s) mnemonic value function 0x0010a fallback trigger, lower 7 s2feb 0 1 disable /sclkx2 trigger (default). enable /sclkx2 trigger. 6scfeb 0 1 disable sclk trigger (default). enable sclk trigger. 5c2feb 0 1 disable c2 trigger (default). enable c2 trigger. 4c4feb 0 1 disable /c4 trigger (default). enable /c4 trigger. 3cmfeb 0 1 disable /c16? trigger (default). enable /c16? trigger. 2cpfeb 0 1 disable /c16+ trigger (default). enable /c16+ trigger. 1cbfeb 0 1 disable ct_c8_b trigger (default). enable ct_c8_b trigger. 0cafeb 0 1 disable ct_c8_a trigger (default). enable ct_c8_a trigger.
36 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.1 control registers (continued) 5.1.8 fallback trigger registers (continued) 5.1.9 watchdog select, c8, and netref registers the watchdog select, c8 register controls the watchdog circuits to monitor the proper frequency for the ct_c8_a and ct_c8_b signals. these signals can take on two values, including 8.192 mhz (ectf mode) and 4.096 mhz (mc1 mode). the watchdog select, netref register controls the watchdog circuits to monitor the proper frequency for the ct_netref1 and ct_netref2 signals. these signals can take on three values depending on system-level clocking architecture, including 8 khz (frame reference), 1.544 mhz (t1 bit clock), and 2.048 mhz (e1 bit clock). table 23. fallback trigger registers (continued) byte address name bit(s) mnemonic value function 0x0010b fallback trigger, upper 7 reserved 0 nop (default). 6d2feb 0 1 disable dpll2 sync trigger (default). enable dpll2 sync trigger. 5d1feb 0 1 disable dpll1 sync trigger (default). enable dpll1 sync trigger. 4n2feb 0 1 disable ct_netref2 trigger (default). enable ct_netref2 trigger. 3n1feb 0 1 disable ct_netref1 trigger (default). enable ct_netref1 trigger. 2fcfeb 0 1 disable /fr_comp trigger (default). enable /fr_comp trigger. 1fbfeb 0 1 disable /ct_frame_b trigger (default). enable /ct_frame_b trigger. 0fafeb 0 1 disable /ct_frame_a trigger (default). enable /ct_frame_a trigger. table 24. watchdog select, c8, netref registers byte address name bit(s) mnemonic value function 0x0010c watchdog select, c8 7:4 cbwsn 0000 0001 ct_c8_b watchdog at 8.192 mhz (default). ct_c8_b watchdog at 4.096 mhz mc1mode. 3:0 cawsn 0000 0001 ct_c8_a watchdog at 8.192 mhz (default). ct_c8_a watchdog at 4.096 mhz mc1mode. 0x0010d watchdog select, netref 7:4 n2wsn 0000 0001 0010 ct_netref2 watchdog at 8 khz (default). ct_netref2 watchdog at 1.544 mhz. ct_netref2 watchdog at 2.048 mhz. 3:0 n1wsn 0000 0001 0010 ct_netref1 watchdog at 8 khz (default). ct_netref1 watchdog at 1.544 mhz. ct_netref1 watchdog at 2.048 mhz.
agere systems inc. 37 data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.1 control registers (continued) 5.1.10 watchdog en register the watchdog en registers are used to enable/disable watchdogs on the individual h-bus clocks and the watch- dogs on the sync inputs of dpll1 and dpll2. table 25. watchdog en registers byte address name bit(s) mnemonic value function 0x0010e watchdog en, lower 7 s2web 0 1 disable /sclkx2 watchdog (default). enable /sclkx2 watchdog. 6scweb 0 1 disable sclk watchdog (default). enable sclk watchdog. 5c2web 0 1 disable c2 watchdog (default). enable c2 watchdog. 4c4web 0 1 disable/c4 watchdog (default). enable/c4 watchdog. 3cmweb 0 1 disable/c16? watchdog (default). enable/c16? watchdog. 2cpweb 0 1 disable/c16+ watchdog (default). enable/c16+ watchdog. 1cbweb 0 1 disable ct_c8_b watchdog (default). enable ct_c8_b watchdog. 0caweb 0 1 disable ct_c8_a watchdog (default). enable ct_c8_a watchdog. 0x0010f watchdog en, upper 7 fsweb 0 1 disable failsafe ref watchdog (default). enable failsafe ref watchdog. 6d2web 0 1 disable dpll2 sync watchdog (default). enable dpll2 sync watchdog. 5d1web 0 1 disable dpll1 sync watchdog (default). enable dpll1 sync watchdog. 4n2web 0 1 disable ct_netref2 watchdog (default). enable ct_netref2 watchdog. 3n1web 0 1 disable ct_netref1 watchdog (default). enable ct_netref1 watchdog. 2fcweb 0 1 disable /fr_comp watchdog (default). enable /fr_comp watchdog. 1 fbweb 0 1 disable /ct_frame_b watchdog (default). enable /ct_frame_b watchdog. 0faweb 0 1 disable /ct_frame_a watchdog (default). enable /ct_frame_a watchdog.
38 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.1 control registers (continued) 5.1.11 failsafe control registers the failsafe control register controls a return from the failsafe state. writes to the failsafe control register trigger the corresponding action, and the set bit(s) are automatically cleared. from the failsafe state, the user can return to either the primary or secondary clock register sets. for more on failsafe, please see section 6.7.2 on page 70. the failsafe enable register controls the enable/disable of failsafe operation. for more on failsafe operation, please see section 6.7.2 on page 70. the failsafe sensitivity register allows the failsafe watchdog timer to be desensitized by either 1, 4, 8, or 16 watch- dog sample clock periods. the ool threshold registers allow for programmable threshold times which indicate the apll1 out-of-lock. reso- lution for the threshold value increments is one 32.768 mhz clock period (30.5 ns). the register contains [count ? 1], a value of 0x0000 yields a 30.5 ns threshold. a value of 0xffff yields a 1.99 ms threshold. for more on ool operation, please see section 6.7.2 on page 70. the ool monitor register allows the user to monitor either the raw apll1 out-of-lock status, or the status flag that indicates that the apll1 has been out-of-lock for more than the threshold defined in the ool threshold regis- ters. table 26. failsafe control register byte address name bit(s) mnemonic value function 0x00114 failsafe control 7:0 fscsr 0000 0000 0000 0001 0000 0010 nop (default). return from failsafe to nonfallback condition. return from failsafe to fallback condition. 0x00115 failsafe enable 7:0 fseer 0000 0000 0000 0001 failsafe disabled. failsafe enabled. 0x00116 failsafe sensitivity 7:0 fsssr 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 failsafe watchdog highest sensitivity. failsafe watchdog + 30.5 ns. failsafe watchdog + 121.0 ns. failsafe watchdog + 244.0 ns. failsafe watchdog + 488.0 ns. 0x00118 ool threshold low 7:0 olllr llll llll failsafe threshold value, low byte. 0x00119 ool threshold high 7:0 olhlr llll llll failsafe threshold value, high byte. 0x0011a ool monitor 7:0 ooler 0000 0000 0000 0001 monitor direct apll1 lock detect at plock. monitor user threshold lock detect at plock.
agere systems inc. 39 data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.2 error and status registers status 7, 6, and 3?0 registers are writable by the user for clearing specific error bits. writing a 1 to any of the bits of these registers will clear the corresponding error bit. the remaining error and status registers are read-only. table 27. error and status register map dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00120 status 3, latched clock errors, upper status 2, latched clock errors, lower status 1, transient clock errors, upper status 0, transient clock errors, lower 0x00124 status 7, system errors reserved reserved status 4 fallback and failsafe status 0x00128 device id, upper device id, lower reserved version id 0x0012c reserved reserved reserved reserved
40 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.2 error and status registers (continued) 5.2.1 clock errors 5.2.1.1 transient clock errors registers the transient clock error registers are used in conjunction with the watchdog en registers and indicate error status for h-bus clocks and dpll1/dpll2 sync inputs whose watchdogs are enabled. the transient indicators are dynamic in nature; if a clock is in error only for a short time and then recovers, the error indication is deasserted when the clock recovers. additionally, an apll1 out-of-lock indicator is provided, and used in conjunction with the failsafe clocking mode. for more details, please see section 6.7.1 on page 64 and section 6.7.2 on page 70. table 28. clock error registers byte address name bit(s) mnemonic value function 0x00120 status 0, transient clock errors, lower 7s2tob 0 1 /sclkx2 no error (default). /sclkx2 error. 6sctob 0 1 sclk no error (default). sclk error. 5c2tob 0 1 c2 no error (default). c2 error. 4c4tob 0 1 /c4 no error (default). /c4 error. 3cmtob 0 1 /c16? no error (default). /c16? error. 2cptob 0 1 /c16+ no error (default). /c16+ error. 1cbtob 0 1 ct_c8_b no error (default). ct_c8_b error. 0catob 0 1 ct_c8_a no error (default). ct_c8_a error. 0x00121 status 1, transient clock errors, upper 7fstob 0 1 failsafe indicator: apll1 reference no error. apll1 reference error. 6d2tob 0 1 dpll2 sync no error (default). dpll2 sync error. 5d1tob 0 1 dpll1 sync no error (default). dpll1 sync error. 4n2tob 0 1 ct_netref2 no error (default). ct_netref2 error. 3n1tob 0 1 ct_netref1 no error (default). ct_netref1 error. 2fctob 0 1 /fr_comp no error (default). /fr_comp error. 1fbtob 0 1 /ct_frame_b no error (default). /ct_frame_b error. 0fatob 0 1 /ct_frame_a no error (default). /ct_frame_a error.
agere systems inc. 41 data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.2 error and status registers (continued) 5.2.1 clock errors (continued) 5.2.1.2 latched clock error register the latched clock error registers capture transient clock errors. the latched indicators capture and hold any tran- sient error status and are used by the clock fallback logic. for more details, see section 6.7 on page 64, and sec- tion 10 on page 90 for more details. table 29. latched clock error registers byte address name bit(s) mnemonic value function 0x00122 status 2, latched clock errors, lower 7s2lob0 1 /sclkx2 no error (default). /sclkx2 error. 6sclob0 1 sclk no error (default). sclk error. 5c2lob0 1 c2 no error (default). c2 error. 4c4lob0 1 /c4 no error (default). /c4 error. 3cmlob0 1 /c16? no error (default). /c16? error. 2cplob0 1 /c16+ no error (default). /c16+ error. 1cblob0 1 ct_c8_b no error (default). ct_c8_b error. 0calob0 1 ct_c8_a no error (default). ct_c8_a error. 0x00123 status 3, latched clock errors, upper 7fslob0 1 failsafe indicator: apll1 reference no error. apll1 reference error. 6d2lob0 1 dpll2 sync no error (default). dpll2 sync error. 5d1lob0 1 dpll1 sync no error (default). dpll1 sync error. 4n2lob0 1 ct_netref2 no error (default). ct_netref2 error. 3n1lob0 1 ct_netref1 no error (default). ct_netref1 error. 2fclob0 1 /fr_comp no error (default). /fr_comp error. 1fblob0 1 /ct_frame_b no error (default). /ct_frame_b error. 0falob0 1 /ct_frame_a no error (default). /ct_frame_a error.
42 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.2 error and status registers (continued) 5.2.2 system status 5.2.2.1 clock fallback status register the upper nibble provides status indicators for clock fallback. fbfob indicates whether the circuit is in a clock fall- back state. fbsop indicates which of five possible states the circuit is in; see section 6.7.1 on page 64 for more details. the lower nibble provides status indicators related to the x and y clock register set active/inactive assignments. xysob indicates which of the clock register sets is active. the remaining bits indicate a pending status for go_clocks, clear_fallback, and force_fallback commands issued (via the fallback control register, 0x00108), which are waiting for a frame sync. table 30. fallback and failsafe status register byte address register name bit(s) mnemonic value function 0x00124 status 4, clock fallback status 7fbfob0 1 indicates not in fallback/failsafe state (default). indicates fallback/failsafe state. 6:4 fbsop 111 000 001 010 011 100 101 fallback state = initial (default). fallback state = primary. fallback state = to_primary. fallback state = secondary. fallback state = to_secondary. failsafe state = fs_1. failsafe state = fs_2. 3xysob0 1 clock register y set is active, x is inactive. clock register x set is active, y is inactive. 2 gopob 0 1 no go_clocks pending (default). go_clocks pending, waiting for frame. 1cfpob0 1 no clear_fallback pending (default). clear_fallback pending, waiting for frame. 0 ffpob 0 1 no force_fallback pending (default). force_fallback pending, waiting for frame.
agere systems inc. 43 data sheet february 2004 ambassador t8110l h.100/h.110 switch 5 operating control and status (continued) 5.2 error and status registers (continued) 5.2.2 system status (continued) 5.2.2.2 device identification registers 5.2.2.3 system device errors these registers identify the device type and revision status, t8110l revision n . table 31. system errors registers byte address register name bit(s) mnemonic value function 0x00127 status 7, system errors 7cfsob 0 1 no error. clock failsafe indicator. 6cfbob 0 1 no error. clock fallback indicator. 5:0 reserved 0 nop. table 32. device identification registers byte address name bit(s) mnemonic value function 0x00128 version id 7:0 veror 0000 0001 revision status (value shown = rev1). 0x0012a device id, lower 7:0 idlor 0001 0000 device id low status 0x10. 0x0012b device id, upper 7:0 idhor 1000 0001 device id high status 0x81.
44 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture 5-9432 (f) figure 5. t8110l main clocking paths 5-9433 (f) figure 6. t8110l netref paths 2.048 mhz 4.096 mhz 8.192 mhz 16.364 mhz frame 32.768 mhz (internal) internal clock phase alignment bit slider controls memories apll1 65.536 mhz apll1 bypass 65.536 mhz sampled frame dpll1 clock source select dpll2 apll2 49.408 mhz to apll2 bypass osc2 xtal2 out xtal2 in/ apll2 rate select dpll2 source and rate div by 4 pri_ref_out pri_ref_in main divide-by-n divide register resource divide-by-n divide register clk sel frame sel dpll1 source and rate osc1 xtal1 out xtal1 in/ clock select /ct_frame_a /ct_frame_b /fr_comp lref[4:7] lref[0:7] ct_netref1 ct_netref2 ct_c8_a ct_c8_b mvip (2 clocks) h- mvip (4 clocks) sc-bus (2 clocks) scsa (2 clocks) 2 or 4 mhz 4 8 1, 5, 3, 6, or 12 mhz x8 x4 osc2 in watchdogs watchdogs programmable inversion prog. inversion mult by 2 watchdog fail safe watchdog frame tclk_out generation sync mux frame osc1 in netref2 divide-by-n divide register net- ref1 sel net- ref2 sel div by 8 (from xtal1) lref[0:7] ct_netref2 ct_netref1 nr2_sel_out nr2_div_in nr2 source select nr1 source select nr2 div select nr1 div select nr1_sel_out nr1_div_in ct_netref2 8 (from xtal2) programmable inversion ct_netref1 programmable inversion programmable inversion programmable inversion netref1 divide-by-n divide register
agere systems inc. 45 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.1 clock input control registers the following registers control the t8110l main clocking paths and netref paths. 6.1.1 main input selector register the main input selector register controls clock and frame input selection. * c2 is allowed as the bit clock input. choices include the following: oscillator/crystal clock = xtal1_in (16.384 mhz), no frame netref1 clock = ct_netref1 (8 khz, 1.544 mhz, or 2.048 mhz), no frame netref2 clock = ct_netref2 (8 khz, 1.544 mhz, or 2.048 mhz), no frame lref individual clock = one of lref[0:7]*, no frame lref paired clock = one of lref[0:3] (2.048 mhz), frame = one of lref[4:7]* h-bus a-clocks clock = ct_c8_a (8.192 mhz), frame = /ct_frame_a (8 khz) * selection of which lref is controlled at register 0x00208. selection of lref polarity is controlled at register 0x0020c. table 33. clock input control register map dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00200 apll1 rate apll1 input selector main divider main input selector 0x00204 apll2 rate reserved resource divider main inversion select 0x00208 dpll1 rate dpll1 input selector reserved lref input select 0x0020c dpll2 rate dpll2 input selector reserved lref inversion select 0x00210 reserved netref1 lref select netref1 divider netref1 input selector 0x00214 reserved netref2 lref select netref2 divider netref2 input selector table 34. main input selector register byte address name bit(s) mnemonic value function 0x00200 main input selector 7:0 ckmsr 0000 0000 0001 0001 0001 0010 0010 0001 0010 0010 0100 0001 0100 0010 0100 0100 0100 1000 1000 0000 1000 0001 1000 0010 1000 0100 1000 1000 select oscillator/crystal (default). select netref1. select netref2. select lref[0:7] individually. select lref[0:3, 4:7] paired. select h-bus a-clocks. select h-bus b-clocks. select mc1 r-clocks. select mc1 l-clocks. select mvip clocks (c2 bit clock)*. select mvip clocks (/c4 bit clock). select h- mvip clocks (/c16 bit clock). select sc-bus clocks 2 mhz. select sc-bus clocks 4/8 mhz.
46 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.1 clock input control registers (continued) h-bus b-clocks clock = ct_c8_b (8.192 mhz), frame = /ct_frame_b (8 khz) mc1 r-clocks clock = inverted ct_c8_a (4.096 mhz), frame = /ct_frame_a (8 khz) mc1 l-clocks clock = inverted ct_c8_b (4.096 mhz), frame = /ct_frame_b (8 khz) mvip clocks clock = /c4 (4.096 mhz), frame = /fr_comp (8 khz) mvip clocks* clock = c2 (2.048 mhz), frame = /fr_comp (8 khz) h- mvip clocks clock = /c16 (16.384 mhz), frame = /fr_comp (8 khz) sc-bus 2 mhz clock = /sclkx2, frame = /fr_comp (8 khz) sc-bus 4/8 mhz clock = sclk, frame = /fr_comp (8 khz) * c2 is allowed as the bit clock input. 6.1.2 main divider register the main divider register contains [divider value ? 1]. a value of 0x00 yields a divide-by-1 function. a value of 0xff yields a divide-by-256 function. 6.1.3 analog pll1 (apll1) input selector register the apll1 input selector register controls apll1 reference input selection. the choices include the following: ! apll1 reference clock = oscillator/4 (4.096 mhz) ! apll1 reference clock = output of the main divider (4.096 mhz or 2.048 mhz) ! apll1 reference clock = output of the resource divider (4.096 mhz or 2.048 mhz) ! apll1 reference clock = output of dpll1 (4.096 mhz or 2.048 mhz) ! apll1 reference clock = input from signal pri_ref_in (4.096 mhz or 2.048 mhz) table 35. main divider register byte address name bit(s) mnemonic value function 0x00201 main divider 7:0 ckmdr llll llll divider value, {0x00 to 0xff} = {div1 to div256}, respectively. table 36. apll1 input selector register byte address name bit(s) mnemonic value function 0x00202 apll1 input selector 7:0 p1isr 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 select oscillator/4 (default). select main divider output. select resource divider output. select dpll1 output. select external input pri_ref_in.
agere systems inc. 47 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.1 clock input control registers (continued) 6.1.4 apll1 rate register the apll1 rate register provides the rate multiplier value to apll1. when apll1 reference clock is at 4.096 mhz, the [x16 (multiplied by)] value must be selected. when apll1 reference clock is at 2.048 mhz, the [x32 (multiplied by)] value must be selected. a [x1 (multiplied by)] value is provided in order to bypass apll1. 6.1.5 main inversion select register the main inversion select register controls programmable inversions at various points within the t8110l main clocking paths and netref paths. internal points allowed for programmable inversion include the following: ! main clock selection clk sel mux output; see figure 5 on page 44. ! netref2 divider output; see figure 6 on page 44. ! netref2 selection mux output. ! netref1 divider output. ! netref1 selection mux output. table 37. apll1 rate register byte address name bit(s) mnemonic value function 0x00203 apll1 rate 7:0 p1rsr 0000 0000 0000 0001 0001 xxxx times 16 (default). times 32. times 1 bypass (lower nibble is don't care). table 38. main inversion select register byte address name bit(s) mnemonic value function 0x00204 main inversion select 7:5 reserved 000 nop (default). 4icmsb 0 1 don't invert main clock selection (default). invert main clock selection. 3n2dsb 0 1 don't invert netref2 divider output (default). invert netref2 divider output. 2 n2ssb 0 1 don't invert netref2 selection (default). invert netref2 selection. 1n1dsb 0 1 don't invert netref1 divider output (default). invert netref1 divider output. 0 n1ssb 0 1 don't invert netref1 selection (default). invert netref1 selection.
48 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.1 clock input control registers (continued) 6.1.6 resource divider register the resource divider register contains [divider value ? 1]. a value of 0x00 yields a divide-by-1 function. a value of 0xff yields a divide-by-256 function. 6.1.7 analog pll2 (apll2) rate register the apll2 rate register provides the rate multiplier value to apll2. when the apll2 reference clock is at 12.352 mhz, the (times 4) value must be selected. when the apll2 reference clock is at 6.176 mhz, the (times 8) value must be selected. a (times 1) value is provided in order to bypass apll2. table 39. resource divider register byte address name bit(s) mnemonic value function 0x00205 resource divider 7:0 ckrdr llll llll divider value, {0x00 to 0xff} = {div1 to div256}, respectively. table 40. apll2 rate register byte address name bit(s) mnemonic value function 0x00207 apll2 rate 7:0 p2rsr 0000 0000 0000 0001 0001 xxxx times 4 (default). times 8. times 1 bypass (lower nibble is don't care).
agere systems inc. 49 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.1 clock input control registers (continued) 6.1.8 lref input select registers the lref input select register is used in conjunction with the main input selector (0x00200) and provides the selection control among the eight lref inputs when the main selection is set for either individual or paired lrefs. the lref inversion select register allows programmable inversion for each lref input. please refer to section 6.4.1.3 on page 60 for further details. table 41. lref input/inversion select registers byte address name bit(s) mnemonic value function 0x00208 lref input select 7:0 lrisr 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 0001 0001 0010 0010 0100 0100 1000 1000 select lref0 (default). select lref0. select lref1. select lref2. select lref3. select lref4. select lref5. select lref6. select lref7. select paired, clock = lref0, frame = lref4. select paired, clock = lref1, frame = lref5. select paired, clock = lref2, frame = lref6. select paired, clock = lref3, frame = lref7. 0x0020c lref inversion select 7ir7sb 0 1 don't invert lref7 (default). invert lref7. 6ir6sb 0 1 don't invert lref6 (default). invert lref6. 5ir5sb 0 1 don't invert lref5 (default). invert lref5. 4ir4sb 0 1 don't invert lref4 (default). invert lref4. 3ir3sb 0 1 don't invert lref3 (default). invert lref3. 2ir2sb 0 1 don't invert lref2 (default). invert lref2. 1ir1sb 0 1 don't invert lref1 (default). invert lref1. 0ir0sb 0 1 don't invert lref0 (default). invert lref0.
50 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.1 clock input control registers (continued) 6.1.9 dpll1 input selector the dpll1 input selector selects one of three sources for dpll1 synchronization input (see section 6.4.2 on page 61), including the following: ! main clock selection clk sel mux output ! main divider output ! resource divider output 6.1.9.1 dpll1 rate register the dpll1 rate register controls the dpll1 output frequency. 6.1.10 dpll2 input selector the dpll2 input selector selects one of five sources for dpll2 synchronization input (see section 6.5.1 on page 63), including the following: ! main clock selection clk sel mux output ! main divider output ! resource divider output ! internal frame ! external input via pri_ref_in signal table 42. dpll1 input selector registers byte address name bit(s) mnemonic value function 0x0020a dpll1 input selector 7:0 d1isr 0000 0000 0000 0001 0000 0010 main selector (default). main divider. resource divider. 0x0020b dpll1 rate 7:0 d1rsr 0000 0000 0000 0001 dpll1 output at 4.096 mhz (default). dpll1 output at 2.048 mhz.
agere systems inc. 51 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.1 clock input control registers (continued) 6.1.10 dpll2 input selector (continued) 6.1.10.1 dpll2 rate register the dpll2 rate register controls the dpll2 output frequency. 6.1.11 netref1 registers the netref1 input selector, netref1 divider, and netref1 lref select registers control the signal paths used to generate ct_netref1 (see figure 6 on page 44). * selection of which lref is controlled at register 0x00212. table 43. dpll2 register byte address name bit(s) mnemonic value function 0x0020e dpll2 input selector 7:0 d2isr 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 main selector (default). main divider. resource divider. t8110l internally generated frame. external input pri_ref_in. 0x0020f dpll2 rate 7:0 d2rsr 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 dpll2 output off (default). dpll2 output at 1.544 mhz. dpll2 output at 3.088 mhz. dpll2 output at 6.176 mhz. dpll2 output at 12.352 mhz. table 44. netref1 registers byte address name bit(s) mnemonic value function 0x00210 netref1 input selector 7:4 n1dsn 0000 0001 divider input = selector output (default). divider input = external input nr1_div_in. 3:0 n1isn 0000 0001 0010 0100 1000 oscillator/xtal1-div-8, 2.048 mhz (default). oscillator/xtal1, 16.384 mhz. ct_netref2 input. lref input*. oscillator/xtal2, 6.176 mhz, or 12.352 mhz. 0x00211 netref1 divider 7:0 nr1dr llll llll divider value, {0x00 to 0xff} = {div1 to div256}, respectively. 0x00212 netref1 lref select 7:0 n1lsr 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 select lref0 (default). select lref0. select lref1. select lref2. select lref3. select lref4. select lref5. select lref6. select lref7.
52 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.1 clock input control registers (continued) 6.1.12 netref2 registers the netref2 input selector, netref2 divider, and netref2 lref select registers control the signal paths used to generate ct_netref2 (see figure 6 on page 44). * selection of which lref is controlled at register 0x00216. table 45. netref2 registers byte address name bit(s) mnemonic value function 0x00214 netref2 input selector 7:4 n2dsn 0000 0001 divider input = selector output (default). divider input = external input nr1_div_in. 3:0 n2isn 0000 0001 0010 0100 1000 oscillator/xtal1-div-8, 2.048 mhz (default). oscillator/xtal1, 16.384 mhz. ct_netref1 input. lref input*. oscillator/xtal2, 6.176 mhz, or 12.352 mhz. 0x00215 netref2 divider 7:0 nr2dr llll llll divider value, {0x00 to 0xff} = {div1 to div256}, respectively. 0x00216 netref2 lref select 7:0 n2lsr 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 select lref0 (default). select lref0. select lref1. select lref2. select lref3. select lref4. select lref5. select lref6. select lref7.
agere systems inc. 53 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.2 clock output control registers the registers listed below control output enable and rate selection of the t8110l clock path outputs. 6.2.1 master output enables register the master output enables register controls the output enables for h-bus and compatibility clocks (cclk) for t8110l clock mastering. a - clocks refers to the combination of ct_c8_a bit clock and /ct_frame_a frame refer- ence. b-clocks refers to the ct_c8_b bit clock and /ct_frame_b frame reference. these programmable enables are used in conjunction with master enable register 0x00103, h-bus clock enables, hckeb. the netref output enables register controls the output enables for ct_netref1 and ct_netref2. these programmable enables are used in conjunction with master enable register 0x00103, h-bus clock enables, hckeb. the cclk output enables register is used in conjunction with register 0x00220 and controls the output enables for various groupings of compatibility clocks, including the following: ! h- mvip bit clock only(/c16) ! mvip clocks (/c4, c2) ! h- mvip clocks (/c16, /c4, c2) ! sc-bus clocks (sclk, /sclkx2) ! /fr_comp compatibility frame reference table 46. clock output control register map dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00220 c8 output rate /fr_comp width netref output enables master output enables 0x00224 sclk output rate tclk select reserved cclk output enables 0x00228 l_sc3 select l_sc2 select l_sc1 select l_sc0 select
54 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.2 clock output control registers (continued) 6.2.1 master output enables register (continued) * overall selection includes all c clocks off, all c clocks on, or select individual groups of c clocks to be enabled, in conjun ction with register 0x00224. 6.2.2 clock output format registers the clock output format registers select the pulse width of the /fr_comp pulse width. note: when the t8110l is slowing to a compatibility bus, the /fr_comp signal must be 122 ns. the t8110l can- not phase align to a 244 ns /fr_comp signal. the c8 output rate register selects the ct_c8_a and ct_c8_b clock output frequency 8.192 mhz for ectf (h1x0) mode, or 4.096 mhz for mc1 mode. the sclk output rate register selects between three sc-bus clock configurations, including the following: ! sclk = 2.048 mhz, /sclkx2 = 4.096 mhz ! sclk = 4.096 mhz, /sclkx2 = 8.192 mhz ! sclk = 8.192 mhz, /sclkx2 = 8.192 mhz (phase shifted from sclk) table 47. master output enables registers byte address name bit(s) mnemonic value function 0x00220 master output enables 7:4 aboen 0000 0001 0010 0011 disable a and b clock outputs (default). enable a clock outputs only. enable b clock outputs only. enable both a and b clock outputs. 3:0 ccoen 0000 0001 0010 disable compatibility (c clock) outputs (default). enable c clocks individually*. enable all c clocks. 0x00221 netref output enables 7:4 n2oen 0000 0001 ct_netref2 disabled (default). ct_netref2 enabled. 3:0 n1oen 0000 0001 ct_netref1 disabled (default). ct_netref1 enabled. 0x00224 cclk output enables 7:4 frsen 0000 0001 /fr_comp disabled (default). /fr_comp enabled. 3:0 ccsen 0000 0001 0010 0011 0100 c-clock bit clocks disabled (default). enable h- mvip bit clock. enable mvip clocks. enable h- mvip all clocks. enable sc-bus clocks.
agere systems inc. 55 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.2 clock output control registers (continued) 6.2.2 clock output format registers (continued) 6.2.3 tclk and l_scx select registers the tclk select register controls the selection of various internally generated clocks for output to the tclk_out signal. the l_scx select registers control the selection of various internally generated clocks for output to the l_sc0, l_sc1, l_sc2, and l_sc3 signals. table 48. clock output format registers byte address name bit(s) mnemonic value function 0x00222 /fr_comp width 7:0 frwsr 0000 0000 0000 0001 /fr_comp width is 122 ns (default). /fr_comp width is 244 ns. 0x00223 c8 output rate 7:4 bcrsn 0000 0001 ct_c8_b output at 8.192 mhz (default). ct_c8_b output at 4.096 mhz, mc1 mode. 3:0 acrsn 0000 0001 ct_c8_a output at 8.192 mhz (default). ct_c8_a output at 4.096 mhz, mc1 mode. 0x00227 sclk output rate 7:0 scrsr 0000 0000 0000 0001 0000 0010 sclk = 2 mhz, /sclkx2 = 4 mhz (default). sclk = 4 mhz, /sclkx2 = 8 mhz. sclk = 8 mhz, /sclkx2 = 8 mhz phase shifted.
56 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.2 clock output control registers (continued) 6.2.3 tclk and l_scx select registers (continued) table 49. tclk select and l_scx select registers byte address name bit(s) mnemonic value function 0x00226 tclk select 7:0 tcosr 0000 0000 0000 0001 0000 0010 0001 0001 0001 0010 0010 0000 0010 0001 0010 0010 0011 0000 0011 0001 0011 0010 0100 0000 0100 0001 0100 0010 0100 0100 0100 1000 0101 0000 0101 0001 0101 0010 0101 0100 0101 1000 1000 0000 1000 0001 1000 0010 1001 0000 1001 0001 1001 0010 tclk output disabled (default). select osc1/xtal1. select osc2/xtal2. select osc1/xtal1 inverted. select osc2/xtal2 inverted. select dpll2 output. select apll1 output, 65.536 mhz. select apll2 output, 49.704 mhz. select dpll2 output inverted. select apll1 output inverted. select apll2 output inverted. select generated 2.048 mhz. select generated 4.096 mhz. select generated 8.192 mhz. select generated 16.384 mhz. select generated 32.768 mhz. select generated 2.048 mhz inverted. select generated 4.096 mhz inverted. select generated 8.192 mhz inverted. select generated 16.384 mhz inverted. select generated 32.768 mhz inverted. select generated frame. select generated ct_netref1. select generated ct_netref2. select generated frame inverted. select generated ct_netref1 inverted. select generated ct_netref2 inverted. 0x00228 (0x00229) (0x0022a) (0x0022b) l_sc0 select l_sc1 select l_sc2 select l_sc3 select 7:0 lc0sr (lc1sr) (lc2sr) (lc3sr) 0000 0000 0000 0001 0001 0001 0100 0000 0100 0001 0100 0010 0100 0100 0100 1000 0101 0000 0101 0001 0101 0010 0101 0100 0101 1000 1000 0000 1000 0001 1000 0010 1001 0000 1001 0001 1001 0010 l_scx output disabled (default). select osc1/xtal1. select osc1/xtal1 inverted. select generated 2.048 mhz. select generated 4.096 mhz. select generated 8.192 mhz. select generated 16.384 mhz. select generated 32.768 mhz. select generated 2.048 mhz inverted. select generated 4.096 mhz inverted. select generated 8.192 mhz inverted. select generated 16.384 mhz inverted. select generated 32.768 mhz inverted. select generated frame. select generated ct_netref1. select generated ct_netref2. select generated frame inverted. select generated ct_netref1 inverted. select generated ct_netref2 inverted.
agere systems inc. 57 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.3 clock register access the t8110l clock control registers, 0x00200?0x002ff, consist of two identical sets of registers, x and y. at any given time, only one set is actually controlling the clocking (denoted as the active set), while the other is in a standby state (inactive set). either set, x or y, may be the active set, as determined by a state machine that tracks the clock fallback control and status and assigns either set to be active accordingly. for more details, see section 6.7.1 on page 64. users may only access one register set at a time. by default, access is allowed to the current inactive set, but access to the active set is allowed via the clock register access select register, 0x00106; see sec- tion 5.1.4 on page 33. 6.4 clock circuit operation?apll1 apll1 can accept either a 4.096 mhz or 2.048 mhz reference clock, and perform a corresponding multiplication function to supply a 65.536 mhz operating clock for the t8110l. additionally, apll1 may be bypassed for circuit diagnostic purposes. please refer to figure 5 on page 44. 6.4.1 main clock selection, bit clock, and frame apll1 clock references are selectable as stand-alone bit clocks, frames, or a pairing of bit clock and frame (see main input selector register, 0x00200). the bit clock output of the main clock selection is available as input to the main divider, resource divider, and dpll1. * mvip , /c4 is typically the bit clock. c2 is selectable as the bit clock as well. ? used when lref pairing is enabled. when using lref pairing, the bit clock should be 2.048 mhz. table 50. bit clock and frame bit clock corresponding 8 khz frame value(s) ct_netref1, ct_netref2 ? 1.544 mhz (t1), 2.048 mhz (e1) na ct_netref1, ct_netref2 8 khz ct_c8_a /ct_frame_a 8.192 mhz (ectf), 4.096 mhz (mc1) ct_c8_b /ct_frame_b 8.192 mhz (ectf), 4.096 mhz (mc1) /c16 /fr_comp 16.384 mhz (h- mvip ) /c4 /fr_comp 4.096 mhz ( mvip ) c2 /fr_comp 2.048 mhz ( mvip *) sclk /fr_comp 2.048 mhz, 4.096 mhz, 8.192 mhz (sc-bus) /sclkx2 /fr_comp 4.096 mhz, 8.192 mhz (sc-bus) lref[0] lref[4] ? system-specific lref[1] lref[5] ? system-specific lref[2] lref[6] ? system-specific lref[3] lref[7] ? system-specific lref[4] ? system-specific lref[5] ? system-specific lref[6] ? system-specific lref[7] ? system-specific
58 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.4 clock circuit operation?apll1 (continued) 6.4.1 main clock selection, bit clock, and frame (continued) 6.4.1.1 watchdog timers a set of watchdog timers is available for all h1x0, h- mvip , mvip , and sc-bus clocks. no watchdogs are available for lref[7:0] directly; however, the lref inputs may be monitored indirectly via watchdogs on the dpll1 and dpll2 sync inputs, or via the failsafe mechanism; see section 6.7.2 on page 70. the watchdogs sample the incoming clocks at 32.768 mhz (derived from the xtal1 crystal) and monitor for loss of signal, as shown below. table 51. watchdog timer description watchdog signal, value description h1x0 clock monitors* ct_c8_a at 8.192 mhz ct_c8_b at 8.192 mhz ectf mode. checks for ct_c8 rising edge within a 35 ns window of its expected arrival. ct_c8_a at 4.096 mhz ct_c8_b at 4.096 mhz mc1 mode. monitors for loss of signal (falling edges). frame monitors /ct_frame_a /ct_frame_b /fr_comp monitors for 8 khz frequency. detects frame overflow (i.e., next frame pulse too late) and frame underflow (i.e., next frame pulse too early). netref monitors* ct_netref1 at 1.544 mhz ct_netref2 at 1.544 mhz netref is t1 bit clock. monitors for loss of signal (rising or falling edges). ct_netref1 at 2.048 mhz ct_netref2 at 2.048 mhz netref is e1 bit clock. monitors for loss of signal (rising or falling edges). ct_netref1 at 8 khz ct_netref2 at 8 khz netref is 8 khz frame reference. monitors for 8 khz frequency. detects frame overflow (i.e., next frame pulse too late) and frame underflow (i.e., next frame pulse too early). compatibility clock monitors /c16 at 16.384 mhz /c4 at 4.096 mhz c2 at 2.048 mhz sclk, /sclkx2 at any of their defined values. gross loss-of-signal detector?clocks are sampled and normalized to 1.024 mhz. it can take up to 976 ns for these watchdog timers to detect loss of a compatibility clock. dpll1, dpll2 sync monitors ? output of mux selector to the sync input of each dpll (8 khz) monitors for 8 khz frequency. detects frame overflow (i.e., next frame pulse too late) and frame underflow (i.e., next frame pulse too early). * user selects frequency at which to monitor the ct_c8 clocks via register 0x0010c, watchdog select, c8. ? dpll sync reference is expected to be 8 khz.
agere systems inc. 59 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.4 clock circuit operation?apll1 (continued) 6.4.1 main clock selection, bit clock, and frame (continued) 6.4.1.2 frame center sampling frame center samples are used in order to phase-align the incoming frame reference to the internally generated frame reference; see section 6.4.5.1 on page 62. the incoming frame reference signal is sampled with a recov- ered clock (output of the apll1 feedback divider) to determine the frame center. frame center sampling is only relevant when the main clock selection is based on a paired bit clock/frame reference, as follows. table 52. frame center sampling frame signal corresponding bit clock sample clock /ct_frame_a ct_c8_a recovered 8.192 mhz, rising edge. /ct_frame_b ct_c8_b recovered 8.192 mhz, rising edge. /fr_comp /c16 (h- mvip ) or /c4 ( mvip ) or c2 ( mvip ) recovered 4.096 mhz, falling edge. /fr_comp sclk or /sclkx2 (sc-bus) recovered 2.048 mhz, rising edge. lref[4] lref[0] recovered 2.048 mhz, rising edge. lref[5] lref[1] recovered 2.048 mhz, rising edge. lref[6] lref[2] recovered 2.048 mhz, rising edge. lref[7] lref[3] recovered 2.048 mhz, rising edge.
60 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.4 clock circuit operation?apll1 (continued) 6.4.1 main clock selection, bit clock, and frame (continued) 6.4.1.3 lref pair polarity configuration the t8110l may derive its clocking from an lref pair, which is compromised of a frame pulse and a 2.048 mhz bit clock. in order to achieve proper phase alignment when deriving clocking from lref pairs, the t8110l must be provided with a frame pulse and bit clock with polarities as shown below. figure 7. t8110l required frame pulse and bit clock with polarities if the frame pulse and bit clock cannot be externally provided with the proper polarities, the polarities can be inter- nally adjusted via the main inversion select register (0x204) and the lref inversion select register (0x20c). the main inversion select register will allow inversion of only the bit clock, while the lref inversion select register allows any lref signal to be inverted. note: once the frame pulse and bit clock polarity have been properly configured, they must not be changed while the t8110l is deriving clocking from the lref pair. master frame (lref 7/6/5/4) master bit clock (lref 3/2/1/0) slave frame frame center master frame signal may be either 122 ns or 244 ns wide. the output frame signal length is programmable. (see section 8 of the t8110 data sheet.)
agere systems inc. 61 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.4 clock circuit operation?apll1 (continued) 6.4.2 main and resource dividers two independently programmable dividers are available to divide down the main clock selection signal. the func- tion ranges from divide-by-1 (bypass) to divide-by-256. ! for binary divider values of 1, 2, 4, 8, 16, 32, 64, 128, and 256, the output is 50% duty cycle. ! for a divider value of 193, the output is almost 50% duty cycle (low-level duration is one clock cycle shorter than high-level duration). ! for all other divider values, the output is a pulse whose width is one full period of the main clock selection signal. output of both dividers is available to the dpll1 and the apll1 reference selector. the output of the main divider is also available at the pri_ref_out chip output. both dividers are reset whenever a changeover between x and y clock register sets is detected; see section 6.3 on page 57. this allows for immediate loading of the newly activated divider register values. 6.4.3 dpll1 a digital phase-lock loop is provided to generate a 4.096 mhz or 2.048 mhz reference to apll1, selectable via register 0x0020b (dpll1 rate). the dpll1 operates at 32.768 mhz, derived from the xtal1 crystal input. the dpll1 synchronization source is selectable (register 0x0020a, dpll1 input selector) between the main clock selection signal, the output of the resource divider, or the output of the main divider, and is intended to be pre- sented as an 8 khz frame reference. dpll1 is determined to be in-lock or out-of-lock, based on the state of the output clock when an edge transition is detected at the synchronization source. an out-of-lock condition results in a dpll1 correction, which can either lengthen or shorten its current output clock period by 30.5 ns. 6.4.4 reference selector the apll1 reference clock is selectable between five possible sources via register 0x00202, apll1 input selector. a 4.096 mhz or 2.048 mhz reference must be provided. the five possible sources are shown below: ! xtal1 crystal (16.384 mhz) divided-by-4 ! main divider output ! resource divider output ! dpll1 output ! pri_ref_in external chip input 6.4.5 internal clock generation the main internal functions of t8110l are synchronous to the 65.536 mhz output of apll1. this clock is further divided to generate 32.768 mhz, 16.384 mhz, and 8 khz internal reference signals. additional divide-down values to 8.192 mhz, 4.096 mhz, and 2.048 mhz are generated. these generated clocks are the source for h1x0, h- mvip , mvip , and sc-bus clocks when the t8110l is mastering the bus clocks; see section 6.2 on page 53. these internally generated clocks can either be free-running, or can be aligned to the incoming main selection clock and frame, via a phase alignment circuit (see section 7.4.5.1).
62 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.4 clock circuit operation?apll1 (continued) 6.4.5 internal clock generation (continued) 6.4.5.1 phase alignment phase alignment allows the free-running internally generated clocks to be forced into alignment with the incoming main selection clock and frame, under the following conditions: ! the main selection clock is based on a paired bit clock/frame reference (see section 6.4.1.2 on page 59), and the phase alignment circuit is enabled (via register 0x00107, phase alignment select). the incoming frame center is monitored via the frame center samplers (see section 6.4.1.2 on page 59) and com- pared to the state of the internally generated frame. the circuit determines whether the frame centers are aligned. if not, three possible actions take place as shown below: ! nop: no corrections when phase alignment is disabled. ! snap correction: the internally generated clocks and frame immediately snap into alignment with the incoming frame center. ! slide correction: the internally generated clocks and frame gradually slide into alignment with the incoming frame center, at a rate of one 65.536 mhz clock period per frame. the sliding occurs in one direction only and creates frame periods that are 15.25 ns longer than 125 s until the frames are aligned. please refer to figure 8. 5-9414 (f) a. phase alignment?snap 5-9415 (f) b. phase alignment?slide figure 8. t8110l phase alignment, snap and slide incoming frame center incoming frame center misaligned internal frame center snap alignment realigned internal frame center 125 s incoming bit clock ct_c8_a incoming frame /ct_frame_a internal clock, 8.192 mhz internal frame realigned internal frame center misaligned internal frame center misaligned internal frame center misaligned internal frame center incoming bit clock ct_c8_a incoming frame /ct_frame_a internal clock, 8.192 mhz internal frame 125 s 125 s 125 s 45 ns 30 ns 15 ns slide alignment slide alignment slide alignment
agere systems inc. 63 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.5 clock circuit operation, apll2 apll2 requires either a 6.176 mhz or 12.352 mhz reference clock to produce a 49.408 mhz clock for operating dpll2. a user-supplied rate multiplier (register 0x00207, apll2 rate) provides either a times 8 function (when ref- erence clock = 6.176 mhz) or a times 4 function (when reference clock = 12.352 mhz). additionally, apll2 may be bypassed for circuit diagnostic purposes (see figure 5 on page 44). 6.5.1 dpll2 a second digital phase-lock loop is provided to generate various derivations of t1 operating frequencies, available by selection via the tclk_out output. the possible output frequencies are selectable via register 0x0020f (dpll2 rate) and include 1.544 mhz, 3.088 mhz, 6.176 mhz, and 12.352 mhz. the dpll2 input clock operates at 49.408 mhz from the apll2 output. synchronization sources for dpll2 include the same sources provided to dpll1 (selectable between the main clock selection signal, the output of the resource divider, or the output of the main divider) and two additional sources, including the t8110l internally generated frame signal and the pri_ref_in input. these selections are available via register 0x0020e, dpll2 input selector. dpll2 is deter- mined to be in-lock or out-of-lock based on the state of its output when an edge transition is detected at the syn- chronization source. an out-of-lock condition results in a dpll2 correction, which can either lengthen or shorten its current output clock period by 20.2 ns. 6.6 clock circuit operation, ct_netref generation the t8110l provides two independently programmable paths to generate ct_netref1 and ct_netref2, via registers 0x00210?0x00216. each ct_netref is individually enabled with register 0x00221, netref output enables. each path consists of a source selector mux and a divider circuit (see figure 6 on page 44). 6.6.1 netref source select xtal1 input div 8 (2.048 mhz) xtal1 input (16.384 mhz) xtal2 input (6.176 mhz or 12.352 mhz) lref[7:0] ct_netrefx (the other netref?i.e., ct_netref1 can be derived from ct_netref2, and vise-versa). the output of the source select mux is made available directly to the netref divider, and also to chip output (nr1_sel_out, nr2_sel_out). 6.6.2 netref divider each netref path provides a divider from a divide-by-1 function up to a divide-by-256 function. the clock source for the divider is selectable between the output of the source select mux or from external chip input (nr1_div_in, nr2_div_in). ! for binary divider values of 1, 2, 4, 8, 16, 32, 64, and 128, output is 50% duty cycle. ! for divider values of 256, 193, plus all other nonbinary values, output is a pulse whose width is one-half of a clock period, asserted during the second half of the divider clock period. the netref dividers are reset whenever a changeover between x and y clock register sets is detected (see sec- tion 6.3 on page 57). this allows for immediate loading of the newly activated divider register values.
64 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.7 clock circuit operation?fallback and failsafe fallback is a means to alter the reference source to apll1 by switching between two clock control register sets upon detection of a fallback event. failsafe is a feature to provide a safety net for the reference source to apll1, independent of clock fallback. 6.7.1 clock fallback clock fallback is a means to alter the apll1 reference clock source upon detection of a fallback event and is con- trolled by eight registers, 0x00108?0x0010f (refer to section 5.1.4 on page 33). these registers enable and con- trol the state transitions that determine which of two clock register sets is used to control the apll1 reference clock source (see section 6.1 on page 45 through section 6.3, table 54 on page 67, and figure 10 on page 66). 6.7.1.1 fallback events clock fallback (transition from primary to secondary clock sets) can only occur if the fallback mode is enabled (reg- ister 0x00109, lower nibble) and a fallback event occurs. when enabled, there are three ways to trigger the fallback event: ! software, via a force_fallback command. the user sets bit 2 of the fallback control register, 0x00108, cre- ating a software-invoked fallback event. ! hardware via the fallback trigger enable registers, 0x0010a?0x0010b. user may enable specific watchdog tim- ers and corresponding fallback trigger enable bits. if a watchdog timer indicates a clock error, and its correspond- ing trigger enable bit is set, a hardware-invoked fallback event is produced. ! hardware, legacy modes, via the fallback type select register, 0x00109, upper nibble. the legacy modes are included to maintain backwards compatibility with earlier ambassador devices. user may enable specific watch- dog timers, but the fallback trigger enable registers are ignored. instead, the watchdogs which are allowed to trigger a fallback event are automatically selected based on the state of the main input selector register, 0x00200 (refer to table 53). if a watchdog timer indicates a clock error, and its corresponding trigger enable is selected via the main input selector, a hardware-invoked fallback event is produced.
agere systems inc. 65 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.7 clock circuit operation?fallback and failsafe (continued) 6.7.1 clock fallback (continued) 6.7.1.1 fallback events (continued) 6.7.1.2 fallback scenarios?fixed vs. rotating secondary when clock fallback is enabled (register 0x00109, lower nibble), there are two possible scenarios for transitioning between the primary and secondary clock sets. in a fixed secondary scheme, a fallback event switches the active clock set from primary to secondary. when the fallback event is cleared (via user-invoked clear_fallback), the active clock set returns to primary. in a rotating secondary scheme, a fallback event switches the active clock set from primary to secondary. when the fallback event is cleared, the secondary remains as the new active clock set. in effect, the secondary becomes the new primary, and the primary becomes the new secondary. the concepts are illustrated in the figure below. 5-9420 (f) figure 9. fallback?fixed vs. rotating secondary table 53. legacy mode fallback event triggers main input selector function (register 0x00200) selected watchdog triggers (legacy modes) oscillator/crystal none ct_netref1 netref1 watchdog ct_netref netref2 watchdog lref, individual none lref, paired none h-bus, a clocks ct_c8_a and /ct_frame_a watchdogs h-bus, b clocks ct_c8_b and /ct_frame_b watchdogs mc1, r clocks none mc1, l clocks none mvip clocks (/c4 or c2 bit clock) /c4, c2, and /fr_comp watchdogs h- mvip clocks /c16, /c4, c2, and /fr_comp watchdogs sc-bus clocks (2 mhz or 4/8 mhz) sclk, /sclkx2, and /fr_comp watchdogs secondary register set (x or y) primary register set (x or y) register set y register set x rotating secondary scenario fallback event fallback cleared fallback event fallback event fixed secondary scenario fallback cleared fallback cleared
66 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.7 clock circuit operation?fallback and failsafe (continued) 6.7.1 clock fallback (continued) 6.7.1.1 fallback scenarios?fixed vs. rotating secondary (continued) 5-9422 (f) figure 10. t8110l clock fallback states fallback type ? to_primary (x is the active set, assert fallback flag) secondary (y is the active set) to_secondary (y is the active set, assert fallback flag) primary (x is the active set) initial (y is the active set) reset user command go_clocks fallback enabled and fallback event fallback enabled and fallback event user command clear_fallback rotating secondary fallback type ? mode fixed secondary mode user command clear_fallback rotating secondary mode fixed secondary mode
agere systems inc. 67 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.7 clock circuit operation?fallback and failsafe (continued) 6.7.1 clock fallback (continued) 6.7.1.1 fallback scenarios?fixed vs. rotating secondary (continued) * fallback event; refer to section 6.7.1.1 on page 64. ? fixed, rotating secondary; refer to section 6.7.1.2 on page 65. table 54. clock fallback state description clock fallback state description exit to exit condition initial y is the active clock register set. default value provides xtal1-div-4 reference. primary user issues go_clocks command (set register 0x00108 bit 0). primary x is the active clock register set and controls apll1 refclk. to_secondary fallback is enabled and fallback event* occurs. to_secondary y is the active clock register set and controls apll1 refclk. fallback flag is asserted. primary user issues clear_fallback com- mand (set register 0x00108 bit 1) and fallback type = fixed secondary ? . secondary user issues clear_fallback com- mand (set register 0x00108 bit 1) and fallback type = rotating secondary ? . secondary y is the active clock register set and controls apll1 refclk. to_primary fallback is enabled and fallback event* occurs. to_primary x is the active clock register set and controls apll1 refclk. fallback flag is asserted. secondary user issues clear_fallback com- mand (set register 0x00108 bit 1) and fallback type = fixed secondary ? . primary user issues clear_fallback com- mand (set register 0x00108 bit 1) and fallback type = rotating secondary ? .
68 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.7 clock circuit operation?fallback and failsafe (continued) 6.7.1 clock fallback (continued) 6.7.1.3 h-bus clock enable/disable on fallback the previous ambassador devices allowed a fallback mode (a/b fallback) which automatically allowed an h1x0 bus clock master to detect an error in its own output clock and remove itself from the bus, or a clock slave to detect an error on its incoming clock and promote itself to clock master. the h-bus clocks include: ! a clocks: ct_c8_a, /ct_frame_a ! b clocks: ct_c8_b, /ct_frame_b ! c clocks: /c16, /c4, c2, sclk, /sclkx2, /fr_comp refer to figure 11 and table 55. the t8110l allows for this mode of operation in two ways: register 0x00109(7:4) = 0100: legacy mode, a/b fallback?when this mode is selected, the fallback triggers allowed are predefined based on the main input clock selection, and the state machine which controls h-bus clock enable/disable is activated. register 0x00109(7:4) = 1001: nonlegacy mode?when this mode is selected, the fallback trigger enable registers determine what triggers a fallback, and the state machine which controls h-bus clock enable/disable is activated. figure 11. t8110l h-bus clock enable states the t8110 enters & leaves these states based on master output enable clock register updates, 0x00220 diag_abc = drives a clocks, b clocks and c clocks, no fallback permitted initial diag_abc diag_ab c_only a_only a_master b_only b_master a_error b_error a clocks fail b clocks fail a clocks fail b clocks fail b clocks fail a clocks fail reprogram b clocks reprogram a clocks diagnostic/forced clocking fallback clocking, assumes fallback enabled in cks register diag_ab = drives a clocks and b clocks, no fallback permitted c_only = drives c clocks only, no fallback permitted b_only = drives b clocks, can be promoted to master and drive c clocks in fallbackcondition a_only = drives a clocks, can be promoted to master and drive c clocks in fallbackcondition b_master = drives b & c clocks, all clocks shut off in fallbackcondition a_master = drives a & c clocks, all clocks shut off in fallbackcondition b_error = all clocks shut off, waiting for b clocks to be reprogrammed a_error = all clocks shut off, waiting for a clocks to be reprogrammed
agere systems inc. 69 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.7 clock circuit operation?fallback and failsafe (continued) 6.7.1 clock fallback (continued) 6.7.1.1 h-bus clock enable/disable on fallback (continued) table 55. h-bus clock enable state description h-bus clock enable state description exit to exit condition initial initial condition, waiting for clock output control register program- ming. any of the other states user update of the clock output control regis- ter (0x00220, master output enables). diag_abc t8110l is driving all h-bus clocks (diagnostic mode). initial user update of the clock output control regis- ter (0x00220, master output enables). diag_ab t8110l is driving both the h-bus a and b clocks (diagnostic mode). initial user update of the clock output control regis- ter (0x00220, master output enables). c_only t8110l is driving only the h-bus c clocks. initial user update of the clock output control regis- ter (0x00220, master output enables). a_master t8110l clock output control regis- ters are programmed to drive a clocks and c clocks (t8110l is an a clock master), or t8110l was supplying a backup a clock and has been promoted to a clock master. a_error a clock error on ct_c8_a or /ct_frame_a is detected; disable clock outputs. initial user update of the clock output control regis- ter (0x00220, master output enables). a_only t8110l clock output control regis- ters are programmed to drive a clocks only (t8110l is a b clock slave, and supplies a backup a clock). a_master a clock error on ct_c8_b or /ct_frame_b is detected; promote to a clock master. a_error a clock error on ct_c8_a or /ct_frame_a is detected; disable clock outputs. initial user update of the clock output control regis- ter (0x00220, master output enables). a_error t8110l has detected a clock error while driving the a clocks, and has stopped driving any h bus clocks. initial user update of the clock output control regis- ter (0x00220, master output enables). b_master t8110l clock output control regis- ters are programmed to drive b clocks and c clocks (t8110l is a b clock master), or t8110l was sup- plying a backup b clock and has been promoted to b clock master. b_error a clock error on ct_c8_b or /ct_frame_b is detected; disable clock outputs. initial user update of the clock output control regis- ter (0x00220, master output enables). b_only t8110l clock output control regis- ters are programmed to drive b clocks only (t8110l is an a clock slave, and supplies a backup b clock). b_master a clock error on ct_c8_a or /ct_frame_a is detected; promote to b clock master. b_error a clock error on ct_c8_b or /ct_frame_b is detected; disable clock outputs. initial user update of the clock output control regis- ter (0x00220, master output enables). b_error t8110l has detected a clock error while driving the b clocks, and has stopped driving any h bus clocks. initial user update of the clock output control regis- ter (0x00220, master output enables).
70 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.7 clock circuit operation?fallback and failsafe (continued) 6.7.2 clock failsafe clock failsafe provides a safety net for the apll1 reference clock source and is controlled by three registers, 0x00114?0x00116; see section 5.1.11 on page 38. a failsafe event overrides the active clock control registers and forces the apll1 clock selection to be a fixed 4.096 mhz, derived from the xtal1 crystal, divided by four. transi- tion into one of the failsafe states is independent of clock fallback (i.e., can enter from any state other than ini- tial). transitions out of the failsafe states are by user command and allow re-entry into either a nonfallback (primary or secondary) or a fallback (to_secondary or to_primary) state. refer to table 56 and figure 12. 6.7.2.1 failsafe events clock failsafe (transition from either clock register set to a forced xtal1-div-4 apll1 reference clock) can only occur if the failsafe mode is enabled (register 0x00115, lower nibble), and a failsafe event occurs. a failsafe event is triggered by a watchdog error on the apll1 reference clock (i.e., loss-of-reference). additionally, an out-of-lock (ool) condition is provided for debug purposes. this does not trigger a failsafe event, but does indicate potential difficulty with the apll1. a lock status flag is provided out of apll1, and the ool is defined by exceeding a user-defined threshold value (register 0x00116). the lock status is a flag indicating when apll1 is making a correction to maintain synchronization. the flag is continuously sampled. if enough active flags are sampled in a row to exceed the user-defined threshold, this condition is reported via the system status register (0x00125). 5-9421 (f) figure 12. t8110l clock failsafe states fs_2 failsafe return to nonfallback state failsafe enabled and failsafe event failsafe enabled and failsafe event failsafe return to fallback state fallback type ? to_primary (x is the active set, assert fallback flag) secondary (y is the active set) to_secondary (y is the active set, assert fallback flag) initial (y is the active set) reset user command go_clocks fallback enabled and fallback event fallback enabled and fallback event user command clear_fallback rotating secondary fallback type ? mode fixed secondary mode user command clear_fallback rotating secondary mode fixed secondary mode fs_1 failsafe return to nonfallback state failsafe enabled and failsafe event failsafe enabled and failsafe event failsafe return to fallback state primary (x is the active set)
agere systems inc. 71 data sheet february 2004 ambassador t8110l h.100/h.110 switch 6 clock architecture (continued) 6.7 clock circuit operation?fallback and failsafe (continued) 6.7.2 clock failsafe (continued) 6.7.2.1 failsafe events (continued) table 56. clock failsafe state descriptions clock failsafe state description exit to exit condition fs_1 apll1 refclk is forced to xtal1-div-4. failsafe flag is asserted. primary user issues failsafe_return to nonfallback state command (set register 0x00114 bit 0). to_secondary user issues failsafe_return to fallback state command (set register 0x00114 bit 1). fs_2 apll1 refclk is forced to xtal1-div-4. failsafe flag is asserted. secondary user issues failsafe_return to non-fallback state command (set register 0x00114 bit 0). to_primary user issues failsafe_return to fallback state command (set register 0x00114 bit 1).
72 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 7 frame group and fg i/o there are eight independently programmable t8110l frame group/fgio signals, fg[7:0]. in the frame group mode, the pin is an 8 khz frame reference output, with programmable pulse width, polarity, and delay offset from the internally generated frame reference. in the fgio mode, the pin behaves as a general-purpose register bit, with programmable direction (in or out) and read masking. the fg7 signal allows for an additional mode of oper- ation, providing a timer via a 16-bit programmable counter. 7.1 frame group control registers 7.1.1 fgx lower and upper start registers the fgx lower and upper start registers provide a 12-bit delay offset value for the corresponding frame group bit. offsets are relative to the t8110l internally generated 8 khz frame reference and have a resolution down to one 32.768 mhz clock period (30.5 ns increments). table 57. frame group and fg i/o register map dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00400 fg0 rate fg0 width fg0 upper start fg0 lower start 0x00410 fg1 rate fg1 width fg1 upper start fg1 lower start 0x00420 fg2 rate fg2 width fg2 upper start fg2 lower start 0x00430 fg3 rate fg3 width fg3 upper start fg3 lower start 0x00440 fg4 rate fg4 width fg4 upper start fg4 lower start 0x00450 fg5 rate fg5 width fg5 upper start fg5 lower start 0x00460 fg6 rate fg6 width fg6 upper start fg6 lower start 0x00470 fg7 rate fg7 width fg7 upper start fg7 lower start 0x00474 fg7 mode upper fg7 mode lower fg7 counter high byte fg7 counter low byte 0x00480 reserved fgio r/w fgio read mask fgio data register table 58. fgx lower and upper start registers byte address name bit(s) mnemonic value function 0x00400 0x00410 0x00420 0x00430 0x00440 0x00450 0x00460 0x00470 fg0 lower start (fg1 lower start) (fg2 lower start) (fg3 lower start) (fg4 lower start) (fg5 lower start) (fg6 lower start) (fg7 lower start) 7:0 f0llr (f1llr) (f2llr) (f3llr) (f4llr) (f5llr) (f6llr) (f7llr) llll llll lower 8 bits of 12-bit start offset. 0x00401 (0x00411) (0x00421) (0x00431) (0x00441) (0x00451) (0x00461) (0x00471) fg0 upper start (fg1 upper start) (fg2 upper start) (fg3 upper start) (fg4 upper start) (fg5 upper start) (fg6 upper start) (fg7 upper start) 7:0 f0ulr (f1ulr) (f2ulr) (f3ulr) (f4ulr) (f5ulr) (f6ulr) (f7ulr) 0000 llll upper 4 bits of 12-bit start offset.
agere systems inc. 73 data sheet february 2004 ambassador t8110l h.100/h.110 switch 7 frame group and fg i/o (continued) 7.1 frame group control registers (continued) 7.1.2 fgx width registers the fgx width registers control the polarity and the pulse widths generated for the corresponding frame group bit. the pulse-width programming works in conjunction with the fgx rate registers to provide 1-bit, 2-bit, 4-bit, 1-byte, and 2-byte wide pulses for any of the available frame group rates (see table 59). 7.1.3 fgx rate registers the fgx rate registers either enable fgio operation* or work in conjunction with fgx width registers to provide various width frame group pulses at rates of 2.048 mhz, 4.096 mhz, 8.192 mhz, or 16.384 mhz. * fgio operation is controlled at registers 0x00480?482. refer to section 7.3 on page 75. table 59. fgx width registers byte address name bit(s) mnemonic value function 0x00402 (0x00412) (0x00422) (0x00432) (0x00442) (0x00452) (0x00462) (0x00472) fg0 width (fg1 width) (fg2 width) (fg3 width) (fg4 width) (fg5 width) (fg6 width) (fg7 width) 7f0isb (f1isb) (f2isb) (f3isb) (f4isb) (f5isb) (f6isb) (f7isb) 0 1 generate active-high pulse (default). generate active-low pulse. 6:0 f0wsp (f1wsp) (f2wsp) (f3wsp) (f4wsp) (f5wsp) (f6wsp) (f7wsp) 000 0000 000 0001 000 0010 000 0100 001 0000 010 0000 1-bit wide pulse (default). 1-bit wide pulse. 2-bit wide pulse. 4-bit wide pulse. 1-byte wide pulse. 2-byte wide pulse. table 60. fgx rate registers byte address name bit(s) mnemonic value function 0x00403 (0x00413) (0x00423) (0x00433) (0x00443) (0x00453) (0x00463) (0x00473) fg0 rate (fg1 rate) (fg2 rate) (fg3 rate) (fg4 rate) (fg5 rate) (fg6 rate) (fg7 rate) 7:0 f0rsr (f1rsr) (f2rsr) (f3rsr) (f4rsr) (f5rsr) (f6rsr) (f7rsr) 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0000 1001 off (default). fgio enabled* (not used as a frame group). fgx rate = 2.048 mhz. fgx rate = 4.096 mhz. fgx rate = 8.192 mhz. fgx rate = 16.384 mhz.
74 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 7 frame group and fg i/o (continued) 7.2 fg7 timer option the fg7 signal allows for an added function of a timer output, via a 16-bit programmable counter. 7.2.1 fg7 counter (low and high byte) registers the fg7 counter (low and high byte) registers set the timer value. the timer is actually a divider, so the value entered must be [divider value ? 1], i.e., 0000000000000011 would yield a div-by-4 operation. the fg7 mode lower register enables the timer option, with two clock source options: t8110l internal frame or an external timer clock via the fg6 signal. the fg7 mode upper register controls the shape of the timer pulse. for more details, see sec- tion 7.4.3 on page 79. * normal operation allows frame group or fgio control via registers 0x00470?473. enabling the counter overrides 0x00470?473 set tings. ? square wave is only available when fg7 counter high/low value is a binary multiple 1, 2, 4, 8, 16, etc. other values yield a carry out pulse shape. ? carry out pulse is active for one fg7 timer clock period. programmable pulses are based on t8110l internal 32.768 mhz clock periods. table 61. fg7 counter (low and high byte) registers byte address name bit mnemonic value function 0x00474 fg7 counter, low byte 7:0 fcllr llll llll lower 8 bits of 16-bit counter value. 0x00475 fg7 counter, high byte 7:0 fculr llll llll upper 8 bits of 16-bit counter value. 0x00476 fg7 mode lower 7:0 f7msr 0000 0000 0000 0001 0000 0010 normal operation* (default). enable timer, clock = internal frame. enable timer, clock = external fg6. 0x00477 fg7 mode upper 7 fcisb 0 1 normal fg7 timer output, high pulses (default). inverted fg7 timer output, low pulses. 6:4 f7ssp 000 001 010 100 fg7 timer output off (default). fg7 timer output = square wave ? . fg7 timer output = carry out pulse ? . fg7 timer output = programmable pulse . 3:0 f7wsn 0001 0010 0100 1000 programmable pulse width = 30.5 ns. programmable pulse width = 61.0 ns. programmable pulse width = 91.5 ns. programmable pulse width = 122 ns.
agere systems inc. 75 data sheet february 2004 ambassador t8110l h.100/h.110 switch 7 frame group and fg i/o (continued) 7.3 fgio control registers 7.3.1 fgio data register the fgio data register provides read/write access and write storage to/from any fg signals being used as gen- eral-purpose register bits. writes to fgio work in conjunction with the corresponding fgio enabled settings in the fgx rate registers. reads are maskable, controlled via register 0x00481. 7.3.2 fgio read mask register the fgio read mask register controls the masking of any fg signals being used as general-purpose register bits on a read access to the fgio register. table 62. fgio data register byte address name bit(s) mnemonic value function 0x00480 fgio data register 7 f7iob l fgio bit 7 value. 6 f6iob l fgio bit 6 value. 5 f5iob l fgio bit 5 value. 4 f4iob l fgio bit 4 value. 3 f3iob l fgio bit 3 value. 2 f2iob l fgio bit 2 value. 1 f1iob l fgio bit 1 value. 0 f0iob l fgio bit 0 value. table 63. fgio read mask register byte address name bit(s) mnemonic value function 0x00481 fgio read mask 7 f7meb 0 1 unmask fgio bit 7 (default). mask fgio bit 7, return 0 on a read. 6f6meb 0 1 unmask fgio bit 6 (default). mask fgio bit 6, return 0 on a read. 5f5meb 0 1 unmask fgio bit 5 (default). mask fgio bit 5, return 0 on a read. 4f4meb 0 1 unmask fgio bit 4 (default). mask fgio bit 4, return 0 on a read. 3f3meb 0 1 unmask fgio bit 3 (default). mask fgio bit 3, return 0 on a read. 2f2meb 0 1 unmask fgio bit 2 (default). mask fgio bit 2, return 0 on a read. 1f1meb 0 1 unmask fgio bit 1 (default). mask fgio bit 1, return 0 on a read. 0f0meb 0 1 unmask fgio bit 0 (default). mask fgio bit 0, return 0 on a read.
76 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 7 frame group and fg i/o (continued) 7.3 fgio control registers (continued) 7.3.3 fgio r/w register the fgio r/w register provides direction control for any of the fg signals being used as general-purpose register bits. table 64. fgio r/w register byte address name bit(s) mnemonic value function 0x00482 fgio r/w 7 f7dsb 0 1 fgio bit 7 direction is input (default). fgio bit 7 direction is output. 6f6dsb 0 1 fgio bit 6 direction is input (default). fgio bit 6 direction is output. 5f5dsb 0 1 fgio bit 5 direction is input (default). fgio bit 5 direction is output. 4f4dsb 0 1 fgio bit 4 direction is input (default). fgio bit 4 direction is output. 3f3dsb 0 1 fgio bit 3 direction is input (default). fgio bit 3 direction is output. 2f2dsb 0 1 fgio bit 2 direction is input (default). fgio bit 2 direction is output. 1f1dsb 0 1 fgio bit 1 direction is input (default). fgio bit 1 direction is output. 0f0dsb 0 1 fgio bit 0 direction is input (default). fgio bit 0 direction is output.
agere systems inc. 77 data sheet february 2004 ambassador t8110l h.100/h.110 switch 7 frame group and fg i/o (continued) 7.4 fg circuit operation each of the eight frame group signals fg[7:0] operate independently and have multiple uses. refer to figure 13 below. ! as programmable 8 khz frame reference outputs (frame group) ! as general-purpose register i/o bits (fgio) ! as a programmable timer (fg7 only) ! as external interrupt input signals ! as diagnostic observation points for internal testpoints 5-9428a (f) figure 13. fg[7:0] functional paths master enable register (0x00103) fgx enable logic fg x rate fgio x r/w testpoint diagnostic control t8110l testpoints output enable pulse generator fg x width offset detect fg x upper/ lower start programmable timer (fg7 only) t8110l from fg6 input internal frame addr fg7 mode fg7 counter hi/lo byte fgio x data reg fgio data register writes from register fgio data register reads to register access interface fg x fgio x read mask fg as external interrupt to interrupt controller access interface if direction = output, return the data reg contents on a readback, else return the i/o pin value. fgio x r/w
78 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 7 frame group and fg i/o (continued) 7.4 fg circuit operation (continued) 7.4.1 frame group 8 khz reference generation any of the t8110l fg signals may be used as programmable 8 khz frame reference outputs. there are two sets of control required, an offset delay from internal frame center, and pulse shaping. the offset delay is provided via the fgx upper/lower start address registers. the delay is relative to the t8110l internal frame center, and the 12 bits used allow for 4096 different offsets, in increments of one 32.768 mhz clock period (30.5 ns). pulse shaping is controlled via the fgx width and fgx rate registers. pulses may be programmed to be active-high or active-low. pulse width can be either 1-bit, 2-bit, 4-bit, 1-byte or 2-byte wide (relative to the rate setting*), with allowable rate settings of 2.048 mhz, 4.096 mhz, 8.192 mhz, and 16.384 mhz. *pulse widths are bit times or multiples of bit times, for each applicable rate: rate bit time 2.048 mbits/s 488 ns 4.096 mbits/s 244 ns 8.192 mbits/s 122 ns 16.384 mbits/s 61 ns notes: frame group signals shown with offset = 0 (default). at offset = 0, the pulse starts at frame center. nonzero offsets denote 32.768 mhz period increments (30.5 ns) from frame center. there are up to 4096 increments within an 8 kh z frame period. offsets may be programmed in the range from 0?4095. frame group signals are shown as active high pulses (default)?they may be programmed as active-low pulses. diagram shows frame group pulse widths relative to bit-clock rate and time-slot width. this is applicable for any of the four f rame group data rates (2 mbits/s, 4 mbits/s, 8 mbits/s, or 16 mbits/s). figure 14. frame group 8 khz reference timing 4 3 2 1 0 31, 63, 127 or 255 bitclock rate (2, 4, 8, or 16mhz) timeslot frame center t8110 internal frame fg(x), 1-bit width, offset = 0 fg(x), 2-bit width, offset = 0 fg(x), 1-byte width, offset = 0 fg(x), 2-byte width, offset = 0 fg(x), 4-bit width, offset = 0
agere systems inc. 79 data sheet february 2004 ambassador t8110l h.100/h.110 switch 7 frame group and fg i/o (continued) 7.4 fg circuit operation (continued) 7.4.2 fgio general-purpose bits any of the t8110l fg signals may be used as general-purpose i/o bits. each fg bit used as fgio is configured by enabling the fgio function via the fgx rate register(s) and setting the direction via the appropriate bits in the fgio r/w register. for write access to the fgio, the fgio data register is used to hold data for output to the fg pin(s). read accesses are maskable via the fgio read mask register. for read access from the fgio, the logical state of the fg[7:0] signals is returned if unmasked. if an fgio bit is masked, a read access returns 0. 7.4.3 programmable timer (fg7 only) the fg7 signal can be used as a programmable timer output, via the fg7 mode upper/lower, and fg7 counter high and low byte registers. the fg7 timer is simply a clock divider. the fg7 counter high/low provides a 16-bit [divider value ? 1]. note: [divider value ? 1], i.e., a value of 0000000000000011 yields a div-by-4 operation. the fg7 mode lower register enables the counter and selects between two clock sources into the counter: either the t8110l internal frame (8 khz) or an external clock via the fg6 input. the fg7 mode upper register controls the output pulse shape. the output can be inverted or noninverted and shaped as either a square wave, a carryout pulse, or a programmable-width pulse. ! square wave. this option is applicable only for divide operations that are binary multiples (i.e., div-by-2, div-by- 4, div-by-8, div-by-16, div-by-65536). nonbinary divide operations while square wave is selected result in a car- ryout pulse. ! carryout pulse. the output is a pulse, width = one fg7 timer clock period. ! programmable-width pulse. the timer output is synchronized to the t8110l 32.768 mhz clock domain and can be programmed for 1, 2, 3, or 4, 32.768 mhz clock periods in width (30.5 ns, 61 ns, 91.5 ns, or 122 ns). 7.4.4 fg external interrupts all fg signals are internally connected as inputs to the interrupt controller logic. any fg signal, whether an output or an input, may be used to trigger interrupts. when a t8110l fg signal is used as an externally sourced input into the interrupt controller logic, it must be in input mode (i.e., shut-off, fgx rate register(s) fxrsr = 0000 0000). an fg signal in output mode may also be used for interrupts (i.e., an 8 khz periodic signal, see section 7.4.1 on page 78). the interrupt control registers (0x00600?603) control how the fg inputs are handled (for more details, refer to section 10.1 on page 90). 7.4.5 fg diagnostic test point observation any of the t8110l fg signals may be used to observe a predefined set of internal testpoints. each fg bit used as a testpoint output is enabled via diagnostic register 0x00140, fg testpoint enable. settings in this register override the fgx rate and fgio r/w register, and force the selected bits to be testpoint outputs, see section 11.1 on page 106 and table 88 on page 106.
80 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 8 general-purpose i/o there are eight independent t8110l gpio signals, gp[7:0]. these pins behave as general-purpose register bits, with programmable direction (in or out) and read masking. the gp0 and gp1 signals allow for an additional mode of operation, providing dedicated output signals to indicate a clock and b clock mastering for h.110 bus applica- tions. 8.1 gpio control registers 8.1.1 gpio data register the gpio data register provides read/write access and write storage to/from any gp signals being used as gen- eral-purpose register bits. reads from gpio are maskable, controlled via register 0x00501. table 65. gpio register dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00500 gpio override gpio r/w gpio read mask gpio data register table 66. gpio data register byte address name bit(s) mnemonic value function 0x00500 gpio data register 7 g7iob l gpio bit 7 value. 6 g6iob l gpio bit 6 value. 5 g5iob l gpio bit 5 value. 4 g4iob l gpio bit 4 value. 3 g3iob l gpio bit 3 value. 2 g2iob l gpio bit 2 value. 1 g1iob l gpio bit 1 value. 0 g0iob l gpio bit 0 value.
agere systems inc. 81 data sheet february 2004 ambassador t8110l h.100/h.110 switch 8 general-purpose i/o (continued) 8.1 gpio control registers (continued) 8.1.2 gpio read mask register the gpio read mask register controls the masking of any gp signals being used as general-purpose register bits on a read access to the gpio register. 8.1.3 gpio r/w register the gpio r/w register provides direction control for any of the gp signals being used as general-purpose register bits. table 67. gpio read mask register byte address name bit(s) mnemonic value function 0x00501 gpio read mask 7 g7meb 0 1 unmask gpio bit 7 (default). mask gpio bit 7, return 0 on a read. 6g6meb 0 1 unmask gpio bit 6 (default). mask gpio bit 6, return 0 on a read. 5g5meb 0 1 unmask gpio bit 5 (default). mask gpio bit 5, return 0 on a read. 4g4meb 0 1 unmask gpio bit 4 (default). mask gpio bit 4, return 0 on a read. 3g3meb 0 1 unmask gpio bit 3 (default). mask gpio bit 3, return 0 on a read. 2g2meb 0 1 unmask gpio bit 2 (default). mask gpio bit 2, return 0 on a read. 1g1meb 0 1 unmask gpio bit 1 (default). mask gpio bit 1, return 0 on a read. 0g0meb 0 1 unmask gpio bit 0 (default). mask gpio bit 0, return 0 on a read. table 68. gpio r/w register byte address name bit(s) mnemonic value function 0x00502 gpio r/w 7 g7dsb 0 1 gpio bit 7 direction is input (default). gpio bit 7 direction is output. 6g6dsb 0 1 gpio bit 6 direction is input (default). gpio bit 6 direction is output. 5g5dsb 0 1 gpio bit 5 direction is input (default). gpio bit 5 direction is output. 4g4dsb 0 1 gpio bit 4 direction is input (default). gpio bit 4 direction is output. 3g3dsb 0 1 gpio bit 3 direction is input (default). gpio bit 3 direction is output. 2g2dsb 0 1 gpio bit 2 direction is input (default). gpio bit 2 direction is output. 1g1dsb 0 1 gpio bit 1 direction is input (default). gpio bit 1 direction is output. 0g0dsb 0 1 gpio bit 0 direction is input (default). gpio bit 0 direction is output.
82 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 8 general-purpose i/o (continued) 8.1 gpio control registers (continued) 8.1.4 gpio override register 8.2 gp circuit operation the eight general-purpose i/o group signals gp[7:0] each operate independently and have multiple uses. please refer to figure 15 on page 82. ! as general-purpose register i/o bits (gpio) ! as h.110 bus clock master indicators (gp0, gp1 only) ! as external interrupt input signals ! as diagnostic observation points for internal testpoints 5-9427a (f) figure 15. gp[7:0] functional paths table 69. gpio override register byte address name bit(s) mnemonic value function 0x00503 gpio override 7:2 reserved 0000 0 nop (default). 1g1oeb 0 1 gpio bit 1 is gpio (default). gpio bit 1 b-master indicator output. 0g0oeb 0 1 gpio bit 0 is gpio (default). gpio bit 0 a-master indicator output. master enable register (0x00103) gpx enable logic gpio override gpio x r/w testpoint diagnostic control t8110l testpoints output enable gpio x data reg gpio data register writes from register gpio data register reads to register access interface gp x gpio x read mask gp as external interrupt to interrupt controller access interface gp0: a-clock master indicator (0x00220 bit 4) gp1: b-clock master indicator (0x00220 bit 5) if direction = output, return the data reg contents on a readback, else return the i/o pin value. gpio x r/w
agere systems inc. 83 data sheet february 2004 ambassador t8110l h.100/h.110 switch 8 general-purpose i/o (continued) 8.2 gp circuit operation (continued) 8.2.1 gpio general-purpose bits any of the t8110l gp signals may be used as general-purpose i/o bits. each gp bit used as gpio is configured by setting the direction via the appropriate bits in the gpio r/w register. for write access to the gpio, the gpio data register is used to hold data for output to the gp pin(s). read accesses are maskable via the gpio read mask register. for read access from the gpio, the logical state of the gp[7:0] signals is returned if unmasked. if a gpio bit is masked, a read access returns 0. 8.2.2 gp dual-purpose bits gpio (override) 8.2.2.1 gp h.110 clock master indicators (gp0, gp1 only) an additional function is provided for gp0 and gp1 only, controlled via the gpio override register. gp0 may be used as a dedicated output (set gpio override register bit 0), which transmits the state of the t8110l a clock master enable (register 0x00220, bit 4). this output is intended to drive the external a clock fets required for h.110 bus mastering. gp1 may be used as a dedicated output (set gpio override register bit 1), which transmits the state of the t8110l b clock master enable (register 0x00220, bit 5). this output is intended to drive the external b clock fets required for h.110 bus mastering. 8.2.3 gp external interrupts any of the t8110l gp signals may be used as externally sourced inputs into the interrupt controller logic. each gp bit used as an interrupt input must be shut off by setting the appropriate gpio r/w register bit to be input. the interrupt control registers (0x00604?607) control how the gp inputs are handled. for more details, see section 10.1 on page 90. 8.2.4 gp diagnostic test point observation any of the t8110l gp signals may be used to observe a predefined set of internal testpoints. each gp bit used as a testpoint output is enabled via diagnostic register 0x00142, gp testpoint enable. settings in this register override the gpio r/w register and force the selected bits to be testpoint outputs (refer to section 11.1 on page 106, and table 90 on page 108).
84 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 9 stream rate control there are a total of 64 data streams, divided into 16 stream groups of four streams each, as shown below. the h-bus group operational frequencies are selectable between 2.048 mhz, 4.096 mhz, and 8.192 mhz. the l-bus groups may operate at 2.048 mhz, 4.096 mhz, 8.192 mhz, and 16.384 mhz, which is implemented as multiplexed 8.192 mhz streams. (for more details, see section 9.2.2 on page 86). table 70. t8110l serial stream groupings stream group stream bits h-bus group a ct_d[0:3] h-bus group b ct_d[4:7] h-bus group c ct_d[8:11] h-bus group d ct_d[12:15] h-bus group e ct_d[16:19] h-bus group f ct_d[20:23] h-bus group g ct_d[24:27] h-bus group h ct_d[28:31] l-bus group a ld[0:3] l-bus group b ld[4:7] l-bus group c ld[8:11] l-bus group d ld[12:15] l-bus group e ld[16:19] l-bus group f ld[20:23] l-bus group g ld[24:27] l-bus group h ld[28:31]
agere systems inc. 85 data sheet february 2004 ambassador t8110l h.100/h.110 switch 9 stream rate control (continued) 9.1 h-bus stream rate control registers 9.1.1 h-bus rate registers the h-bus rate registers control the serial data stream rate of operation for each of the h-bus stream groups, a?h. the upper nibble controls groups b, d, f, and h. the lower nibble controls groups a, c, e, and g. 9.2 l-bus stream rate control registers 9.2.1 l-bus rate registers the l-bus rate registers control the serial data stream rate of operation for each of the l-bus stream groups, a?h. the upper nibble controls groups b, d, f, and h. the lower nibble controls groups a, c, e, and g. local streams have a 16.384 mhz rate option (refer to section 9.2.2 on page 86). table 71. h-bus rate registers dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00300 h-bus rate h/g h-bus rate f/e h-bus rate d/c h-bus rate b/a byte address name bit(s) mnemonic value function 0x00300 (0x00301) (0x00302) (0x00303) h-bus rate b/a (h-bus rate d/c) (h-bus rate f/e) (h-bus rate h/g) 7:4 hbrsn (hdrsn) (hfrsn) (hhrsn) 0000 0010 0100 1000 h-bus group b(d, f, h) off (default). h-bus group b(d, f, h) rate = 2.048 mhz. h-bus group b(d, f, h) rate = 4.096 mhz. h-bus group b(d, f, h) rate = 8.192 mhz. 3:0 harsn (hcrsn) (hersn) (hgrsn) 0000 0010 0100 1000 h-bus group a(c, e, g) off (default). h-bus group a(c, e, g) rate = 2.048 mhz. h-bus group a(c, e, g) rate = 4.096 mhz. h-bus group a(c, e, g) rate = 8.192 mhz. table 72. l-bus rate registers dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00320 l-bus rate h/g l-bus rate f/e l-bus rate d/c l-bus rate b/a byte address name bit(s) mnemonic value function 0x00320 (0x00321) (0x00322) (0x00323) l-bus rate b/a (l-bus rate d/c) (l-bus rate f/e) (l-bus rate h/g) 7:4 lbrsn (ldrsn) (lfrsn) (lhrsn) 0000 0010 0100 1000 1001 l-bus group b(d, f, h) off (default). l-bus group b(d, f, h) rate = 2.048 mhz. l-bus group b(d, f, h) rate = 4.096 mhz. l-bus group b(d, f, h) rate = 8.192 mhz. l-bus group b(d, f, h) rate = 16.384 mhz. 3:0 larsn (lcrsn) (lersn) (lgrsn) 0000 0010 0100 1000 1001 l-bus group a(c, e, g) off (default). l-bus group a(c, e, g) rate = 2.048 mhz. l-bus group a(c, e, g) rate = 4.096 mhz. l-bus group a(c, e, g) rate = 8.192 mhz. l-bus group a(c, e, g) rate = 16.384 mhz.
86 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 9 stream rate control (continued) 9.2 l-bus stream rate control registers (continued) 9.2.2 l-bus 16.384 mbits/s operation local stream 16.384 mbits/s operation is implemented as two multiplexed 8.192 mbits/s streams. bits are shifted at 16.384 mhz, and 16 bits are shifted per 8.192 mbits/s time slot (refer to figure 16). this operation makes use of adjacent pairs of the existing single-byte hold and shift registers for local stream operation, with the local even stream assigned as the incoming stream, and the local odd stream assigned as the outgoing stream. pairs are assigned as ld[0,1], ld[2,3], . . . ld[30,31]. when an l-bus group is set to operate at rate of 16.384 mbits/s, the hold and shift circuitry is configured such that the serial output of the even stream shift register feeds the serial input of the odd stream shift register (refer to figure 17). 5-9411 (f) figure 16. local stream 16.384 mbits/s timing 15 6 976 ns (one 8 mbits/s time-slot) time-slot n incoming bits are sampled at the 3/4 point of the bit time 14 13 12 11 10 9 8 7 5 4 3 2 1 0 8.192 mhz 16.384 mhz serial data: l_d[even] (incoming), l_d[odd] (outgoing) offload incoming bytes from time-slot n ? 1 to holding registers, load outgoing bytes for time-slot n to shift registers offload incoming bytes from time-slot n to holding registers, load outgoing bytes for time-slot n + 1 to shift registers
agere systems inc. 87 data sheet february 2004 ambassador t8110l h.100/h.110 switch 9 stream rate control (continued) 9.2 l-bus stream rate control registers (continued) 9.2.2 l-bus 16.384 mbits/s operation (continued) 5-9426 (f) figure 17. local stream 16.384 mbits/s circuit local even stream shift register even stream incoming holding register even stream outgoing holding register odd stream incoming holding register odd stream outgoing holding register ms bit local odd stream shift register ms bit 8 8-bit byte to data memory 8-bit byte from data memory 8 8 8-bit byte to data memory 8-bit byte from data memory 8 (no local even serial output if 16.384 mbits/s operation) outgoing serial data outgoing serial data (odd) incoming serial data (even) (no local odd serial input if 16.384 mbits/s operation) incoming serial data 16.384 mbits/s enable (odd) (even)
88 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 9 stream rate control (continued) 9.2 l-bus stream rate control registers (continued) 9.2.3 16.384 mbits/s local i/o superrate this 16.384 mbits/s rate option is available only on the local i/o streams (i.e., it is not supported as a part of the h.100/h.110 specifications). when applying the superrate option to a local i/o group, the i/o for the group is rede- fined and divided into two pairs of input and output. an input or an output can be selected from each pair, but both can't be used simultaneously. this leads to four possible configurations for each group. note that inputs are always on even signals and outputs are always on odd signals. thus, if all local groups are operated at the superrate, then the application can have 16 lines, all at 16.384 mbits/s, in contrast to the 32 i/o lines at normal rates. figure 18. superrate i/o configuration local i/o pins ld0 ld1 ld2 ld3 group a group a configuration at 2.048, 4.096, or 8.192 mbits/s local i/o pins ld0 ld1 ld2 ld3 group a group a configuration 1 at 16.384 mbits/s superrate local i/o pins ld0 ld1 ld2 ld3 group a group a configuration 2 at 16.384 mbits/s superrate local i/o pins ld0 ld1 ld2 ld3 group a group a configuration 3 at 16.384 mbits/s superrate local i/o pins ld0 ld1 ld2 ld3 group a group a configuration 4 at 16.384 mbits/s superrate
agere systems inc. 89 data sheet february 2004 ambassador t8110l h.100/h.110 switch 9 stream rate control (continued) 9.2 l-bus stream rate control registers (continued) 9.2.4 16.384 mbits/s local i/o superrate the configurations are selected as a consequence of the connection programming. the data is inputted or output- ted as a true 16-bit at 16.384 mbits/s signal. programming a 16-bit connection requires two separate byte connec- tions, one for the ms-byte and the other for the ls-byte. note: n = even number, m = integer. figure 19. relationship between 8.192 mbits/s and 16.384 mbits/s time slots thus, programming a connection to stream n + 1 is programming a connection to the ms-byte on output pin n + 1 and programming a connection to stream n is programming a connection to the ls-byte on output pin n + 1. simi- larly, programming a connection from stream n + 1 is programming a connection from the ms-byte on input pin n and programming a connection from stream n is programming a connection from the ls-byte on input pin n. (an easier way to remember this is that the even/odd identifier becomes the ms-byte/ls-byte identifier.) as a consequence of this arrangement, the t8110l permits byte-packing at the superrate in analogous manner to subrate bit-packing. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 programming a connection for stream n + 1, time slot m writes to/reads from here programming a connection for stream n, time slot m writes to/reads from here superrate streampair n/n + 1, timeslot m if input use stream n, if output use stream n + 1 7 6 5 4 3 2 1 0 8.192 mbits/s stream n, timeslot m and 8.192 mbits/s stream n + 1, timeslot m 122 ns 61 ns 8.192 mbits/s input data bits are sampled at 3/4 point (91 ns) of the 122 ns bit time 16.384 mbits/s input data bits are sampled at 3/4 point (45 ns) of the 61 ns bit time
90 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control 10.1 interrupt control registers 10.1.1 interrupts via external fg[7:0] registers 10.1.1.1 fgio interrupt pending register the fgio interrupt pending register stores detected interrupts via the fg[7:0] signals. the user can clear specific pending bits by writing 1 to that bit (write 1 to clear). interrupts via these signals are maskable via the fgio inter- rupt enable register. table 73. interrupt control register map dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00600 fgio polarity reserved fgio interrupt enable fgio interrupt pending 0x00604 gpio polarity reserved gpio interrupt enable gpio interrupt pending 0x00608 system interrupt enable high system interrupt enable low system interrupt pending high system interrupt pending low 0x0060c clock interrupt enable high clock interrupt enable low clock interrupt pending high clock interrupt pending low 0x00610 clkerr output select syserr output select reserved arbitration control 0x00614 clkerr pulse width syserr pulse width reserved reserved 0x006fc reserved reserved in-service, high in-service, low table 74. fgio interrupt pending registers byte address name bit(s) mnemonic value function 0x00600 fgio interrupt pending 7 jf7ob 0 1 no pending interrupts via fg7 (default). pending interrupt via fg7. 6jf6ob 0 1 no pending interrupts via fg6 (default). pending interrupt via fg6. 5jf5ob 0 1 no pending interrupts via fg5 (default). pending interrupt via fg5. 4jf4ob 0 1 no pending interrupts via fg4 (default). pending interrupt via fg4. 3jf3ob 0 1 no pending interrupts via fg3 (default). pending interrupt via fg3. 2jf2ob 0 1 no pending interrupts via fg2 (default). pending interrupt via fg2. 1jf1ob 0 1 no pending interrupts via fg1 (default). pending interrupt via fg1. 0jf0ob 0 1 no pending interrupts via fg0 (default). pending interrupt via fg0.
agere systems inc. 91 data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.1 interrupts via external fg[7:0] registers (continued) 10.1.1.1 fgio interrupt pending register (continued) the fgio edge/level and fgio polarity registers control how interrupts are interpreted on the gp[7:0] signals (negative edge, positive edge, low level, or high level). table 74. fgio interrupt pending registers (continued) byte address name bit(s) mnemonic value function 0x00601 fgio interrupt enable 7 jf7eb 0 1 disable (mask) interrupts via fg7 (default). enable (unmask) interrupts via fg7. 6jf6eb 0 1 disable (mask) interrupts via fg6 (default). enable (unmask) interrupts via fg6. 5jf5eb 0 1 disable (mask) interrupts via fg5 (default). enable (unmask) interrupts via fg5. 4jf4eb 0 1 disable (mask) interrupts via fg4 (default). enable (unmask) interrupts via fg4. 3jf3eb 0 1 disable (mask) interrupts via fg3 (default). enable (unmask) interrupts via fg3. 2jf2eb 0 1 disable (mask) interrupts via fg2 (default). enable (unmask) interrupts via fg2. 1jf1eb 0 1 disable (mask) interrupts via fg1 (default). enable (unmask) interrupts via fg1. 0jf0eb 0 1 disable (mask) interrupts via fg0 (default). enable (unmask) interrupts via fg0. table 75. fgio edge/level and polarity registers byte address name bit(s) mnemonic value function 0x00603 fgio polarity 7 if7sb 0 1 fg7 interrupts are negative edge or low level (default). fg7 interrupts are positive edge or high level. 6if6sb 0 1 fg6 interrupts are negative edge or low level (default). fg6 interrupts are positive edge or high level. 5if5sb 0 1 fg5 interrupts are negative edge or low level (default). fg5 interrupts are positive edge or high level. 4if4sb 0 1 fg4 interrupts are negative edge or low level (default). fg4 interrupts are positive edge or high level. 3if3sb 0 1 fg3 interrupts are negative edge or low level (default). fg3 interrupts are positive edge or high level. 2if2sb 0 1 fg2 interrupts are negative edge or low level (default). fg2 interrupts are positive edge or high level. 1if1sb 0 1 fg1 interrupts are negative edge or low level (default). fg1 interrupts are positive edge or high level. 0if0sb 0 1 fg0 interrupts are negative edge or low level (default). fg0 interrupts are positive edge or high level.
92 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.2 interrupts via external gp[7:0] 10.1.2.1 gpio interrupt pending register the gpio interrupt pending register stores detected interrupts via the gp[7:0] signals. the user can clear specific pending bits by writing 1 to that bit (write 1 to clear). interrupts via these signals are maskable via the gpio inter- rupt enable register. table 76. gpio interrupt pending register byte address name bit(s) mnemonic value function 0x00604 gpio interrupt pending 7 jg7ob 0 1 no pending interrupts via gp7 (default). pending interrupt via gp7. 6 jg6ob 0 1 no pending interrupts via gp6 (default). pending interrupt via gp6. 5 jg5ob 0 1 no pending interrupts via gp5 (default). pending interrupt via gp5. 4 jg4ob 0 1 no pending interrupts via gp4 (default). pending interrupt via gp4. 3 jg3ob 0 1 no pending interrupts via gp3 (default). pending interrupt via gp3. 2 jg2ob 0 1 no pending interrupts via gp2 (default). pending interrupt via gp2. 1 jg1ob 0 1 no pending interrupts via gp1 (default). pending interrupt via gp1. 0 jg0ob 0 1 no pending interrupts via gp0 (default). pending interrupt via gp0. 0x00605 gpio interrupt enable 7 jg7eb 0 1 disable (mask) interrupts via gp7 (default). enable (unmask) interrupts via gp7. 6jg6eb 0 1 disable (mask) interrupts via gp6 (default). enable (unmask) interrupts via gp6. 5jg5eb 0 1 disable (mask) interrupts via gp5 (default). enable (unmask) interrupts via gp5. 4jg4eb 0 1 disable (mask) interrupts via gp4 (default). enable (unmask) interrupts via gp4. 3jg3eb 0 1 disable (mask) interrupts via gp3 (default). enable (unmask) interrupts via gp3. 2jg2eb 0 1 disable (mask) interrupts via gp2 (default). enable (unmask) interrupts via gp2. 1jg1eb 0 1 disable (mask) interrupts via gp1 (default). enable (unmask) interrupts via gp1. 0jg0eb 0 1 disable (mask) interrupts via gp0 (default). enable (unmask) interrupts via gp0.
agere systems inc. 93 data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.2 interrupts via external gp[7:0] (continued) 10.1.2.2 gpio edge/level and gpio polarity registers the gpio edge/level and gpio polarity registers control how interrupts are interpreted on the gp[7:0] signals (negative edge, positive edge, low level, or high level). 10.1.3 interrupts via internal system errors table 77. gpio edge/level and gpio polarity registers byte address name bit(s) mnemonic value function 0x00607 gpio polar- ity 7ig7sb 0 1 gp7 interrupts are negative edge or low level (default). gp7 interrupts are positive edge or high level. 6ig6sb 0 1 gp6 interrupts are negative edge or low level (default). gp6 interrupts are positive edge or high level. 5ig5sb 0 1 gp5 interrupts are negative edge or low level (default). gp5 interrupts are positive edge or high level. 4ig4sb 0 1 gp4 interrupts are negative edge or low level (default). gp4 interrupts are positive edge or high level. 3ig3sb 0 1 gp3 interrupts are negative edge or low level (default). gp3 interrupts are positive edge or high level. 2ig2sb 0 1 gp2 interrupts are negative edge or low level (default). gp2 interrupts are positive edge or high level. 1ig1sb 0 1 gp1 interrupts are negative edge or low level (default). gp1 interrupts are positive edge or high level. 0if0sb 0 1 gp0 interrupts are negative edge or low level (default). gp0 interrupts are positive edge or high level. table 78. system error interrupt assignments system interrupt bit description sys15 clock failsafe indicator. sys14 clock fallback indicator. sys13 reserved. sys12 reserved. sys11 reserved. sys10 reserved. sys9 reserved. sys8 reserved. sys7 reserved. sys6 reserved. sys5 reserved. sys4 reserved. sys3 reserved. sys2 reserved. sys1 reserved. sys0 reserved.
94 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.4 system interrupt pending high/low registers the system interrupt pending high/low registers store detected interrupts via the internal system error signals. the user can clear specific bits by writing 1 to that bit (write 1 to clear). table 79. system interrupt pending high/low registers byte address name bit(s) mnemonic value function 0x00608 system interrupt pending low 7 js7ob 0 1 no pending interrupts via sys7 (default). pending interrupt via sys7. 6js6ob 0 1 no pending interrupts via sys6 (default). pending interrupt via sys6. 5js5ob 0 1 no pending interrupts via sys5 (default). pending interrupt via sys5. 4js4ob 0 1 no pending interrupts via sys4 (default). pending interrupt via sys4. 3js3ob 0 1 no pending interrupts via sys3 (default). pending interrupt via sys3. 2js2ob 0 1 no pending interrupts via sys2 (default). pending interrupt via sys2. 1js1ob 0 1 no pending interrupts via sys1 (default). pending interrupt via sys1. 0js0ob 0 1 no pending interrupts via sys0 (default). pending interrupt via sys0. 0x00609 system interrupt pending high 7jsfob 0 1 no pending interrupts via sys15 (default). pending interrupt via sys15. 6jseob 0 1 no pending interrupts via sys14 (default). pending interrupt via sys14. 5jsdob 0 1 no pending interrupts via sys13 (default). pending interrupt via sys13. 4jscob 0 1 no pending interrupts via sys12 (default). pending interrupt via sys12. 3jsbob 0 1 no pending interrupts via sys11 (default). pending interrupt via sys11. 2jsaob 0 1 no pending interrupts via sys10 (default). pending interrupt via sys10. 1js9ob 0 1 no pending interrupts via sys9 (default). pending interrupt via sys9. 0js8ob 0 1 no pending interrupts via sys8 (default). pending interrupt via sys8.
agere systems inc. 95 data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.5 system interrupt enable high/low registers the system interrupt enable high/low registers allow for masking of interrupts via the internal system error signals. table 80. system interrupt enable high/low registers byte address name bit(s) mnemonic value function 0x0060a system interrupt enable low 7 js7eb 0 1 disable (mask) interrupts via sys7 (default). enable (unmask) interrupts via sys7. 6 js6eb 0 1 disable (mask) interrupts via sys6 (default). enable (unmask) interrupts via sys6. 5 js5eb 0 1 disable (mask) interrupts via sys5 (default). enable (unmask) interrupts via sys5. 4 js4eb 0 1 disable (mask) interrupts via sys4 (default). enable (unmask) interrupts via sys4. 3 js3eb 0 1 disable (mask) interrupts via sys3 (default). enable (unmask) interrupts via sys3. 2 js2eb 0 1 disable (mask) interrupts via sys2 (default). enable (unmask) interrupts via sys2. 1 js1eb 0 1 disable (mask) interrupts via sys1 (default). enable (unmask) interrupts via sys1. 0 js0eb 0 1 disable (mask) interrupts via sys0 (default). enable (unmask) interrupts via sys0. 0x0060b system interrupt enable high 7jsfeb0 1 disable (mask) interrupts via sys15 (default). enable (unmask) interrupts via sys15. 6jseeb0 1 disable (mask) interrupts via sys14 (default). enable (unmask) interrupts via sys14. 5 jsdeb 0 1 disable (mask) interrupts via sys13 (default). enable (unmask) interrupts via sys13. 4 jsceb 0 1 disable (mask) interrupts via sys12 (default). enable (unmask) interrupts via sys12. 3jsbeb0 1 disable (mask) interrupts via sys11 (default). enable (unmask) interrupts via sys11. 2jsaeb0 1 disable (mask) interrupts via sys10 (default). enable (unmask) interrupts via sys10. 1 js9eb 0 1 disable (mask) interrupts via sys9 (default). enable (unmask) interrupts via sys9. 0 js8eb 0 1 disable (mask) interrupts via sys8 (default). enable (unmask) interrupts via sys8.
96 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.6 interrupts via internal clock errors table 81. clock error interrupt assignments clock interrupt bit description clk15 failsafe indicator?apll1 reference error. clk14 dpll2 sync input error. clk13 dpll1 sync input error. clk12 ct_netref2 error. clk11 ct_netref1 error. clk10 /fr_comp error. clk9 /ct_frame_b error. clk8 /ct_frame_a error. clk7 /sclkx2 error. clk6 sclk error. clk5 c2 error. clk4 /c4 error. clk3 /c16? error. clk2 /c16+ error. clk1 ct_c8_b error. clk0 ct_c8_a error.
agere systems inc. 97 data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.7 clock interrupt pending high/low registers the clock interrupt pending high/low registers store detected interrupts via the internal clock error signals (refer to section 5.2.1 on page 40). the user can clear specific bits by writing 1 to that bit (write 1 to clear). table 82. clock interrupt pending high/low registers byte address name bit(s) mnemonic value function 0x0060c clock interrupt pending low 7 jc7ob 0 1 no pending interrupts via clk7 (default). pending interrupt via clk7. 6jc6ob0 1 no pending interrupts via clk6 (default). pending interrupt via clk6. 5jc5ob0 1 no pending interrupts via clk5 (default). pending interrupt via clk5. 4jc4ob0 1 no pending interrupts via clk4 (default). pending interrupt via clk4. 3jc3ob0 1 no pending interrupts via clk3 (default). pending interrupt via clk3. 2jc2ob0 1 no pending interrupts via clk2 (default). pending interrupt via clk2. 1jc1ob0 1 no pending interrupts via clk1 (default). pending interrupt via clk1. 0jc0ob0 1 no pending interrupts via clk0 (default). pending interrupt via clk0. 0x0060d clock interrupt pending high 7jcfob0 1 no pending interrupts via clk15 (default). pending interrupt via clk15. 6jceob0 1 no pending interrupts via clk14 (default). pending interrupt via clk14. 5 jcdob 0 1 no pending interrupts via clk13 (default). pending interrupt via clk13. 4 jccob 0 1 no pending interrupts via clk12 (default). pending interrupt via clk12. 3jcbob0 1 no pending interrupts via clk11 (default). pending interrupt via clk11. 2jcaob0 1 no pending interrupts via clk10 (default). pending interrupt via clk10. 1jc9ob0 1 no pending interrupts via clk9 (default). pending interrupt via clk9. 0jc8ob0 1 no pending interrupts via clk8 (default). pending interrupt via clk8.
98 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.8 clock interrupt enable high/low registers the clock interrupt enable high/low registers allow for masking of interrupts via the internal clock error signals. table 83. clock interrupt enable high/low registers byte address name bit(s) mnemonic value function 0x0060e clock interrupt enable low 7jc7eb 0 1 disable (mask) interrupts via clk7 (default). enable (unmask) interrupts via clk7. 6jc6eb 0 1 disable (mask) interrupts via clk6 (default). enable (unmask) interrupts via clk6. 5jc5eb 0 1 disable (mask) interrupts via clk5 (default). enable (unmask) interrupts via clk5. 4jc4eb 0 1 disable (mask) interrupts via clk4 (default). enable (unmask) interrupts via clk4. 3jc3eb 0 1 disable (mask) interrupts via clk3 (default). enable (unmask) interrupts via clk3. 2jc2eb 0 1 disable (mask) interrupts via clk2 (default). enable (unmask) interrupts via clk2. 1jc1eb 0 1 disable (mask) interrupts via clk1 (default). enable (unmask) interrupts via clk1. 0jc0eb 0 1 disable (mask) interrupts via clk0 (default). enable (unmask) interrupts via clk0. 0x0060f clock interrupt enable high 7jcfeb 0 1 disable (mask) interrupts via clk15 (default). enable (unmask) interrupts via clk15. 6 jceeb 0 1 disable (mask) interrupts via clk14 (default). enable (unmask) interrupts via clk14. 5 jcdeb 0 1 disable (mask) interrupts via clk13 (default). enable (unmask) interrupts via clk13. 4 jcceb 0 1 disable (mask) interrupts via clk12 (default). enable (unmask) interrupts via clk12. 3 jcbeb 0 1 disable (mask) interrupts via clk11 (default). enable (unmask) interrupts via clk11. 2 jcaeb 0 1 disable (mask) interrupts via clk10 (default). enable (unmask) interrupts via clk10. 1jc9eb 0 1 disable (mask) interrupts via clk9 (default). enable (unmask) interrupts via clk9. 0jc8eb 0 1 disable (mask) interrupts via clk8 (default). enable (unmask) interrupts via clk8.
agere systems inc. 99 data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.9 interrupt servicing registers 10.1.9.1 arbitration control register the arbitration control register allows for four modes of interrupt control operation as shown below: ! disabled. this mode bypasses any interrupt controller operation. no fg or gp inputs are allowed as external interrupt inputs. syserr assertion is a simple logical or of the internal system error bits. clkerr assertion is a simple logical or of the internal clock error bits. ! flat. this mode treats all 48 possible inputs (eight from external fg[7:0], eight from external gp[7:0], 16 from internal system errors, 16 from internal clock errors) with equal weight, and queues them for in-service via a round-robin arbitration. ! tier, no pre-empting. this mode assigns three priority levels. the highest level is internal clock errors clk[15:0]; next level is internal system errors sys[15:0]; lowest level is external errors fg[7:0] and gp[7:0]. arbitration pri- ority encodes between the three levels. multiple interrupts within a level are queued round-robin. ! tier, with pre-empting. this mode is the same as tier, with the added ability to pre-empt a current in-service inter- rupt according to the three priority levels. 10.1.9.2 syserr and clkerr output select register the syserr output select register controls how the syserr signal is asserted (active-high level, active-low level, active-high pulse, or active-low pulse). the syserr pulse-width register controls how wide the syserr pulse is (when selected output format = high or low pulse). value corresponds to the number of 32.768 mhz periods ? 1. the clkerr output select register controls how the clkerr signal is asserted (active-high level, active-low level, active-high pulse, or active-low pulse). the clkerr pulse-width register controls how wide the clkerr pulse is (when selected output format = high or low pulse). value corresponds to the number of 32.768 mhz periods ? 1. table 84. arbitration control register byte address name bit(s) mnemonic value function 0x00610 arbitration control 7:0 jamsr 0000 0000 0000 0001 0000 0010 0001 0010 disable interrupt controller (default). flat structure (round-robin arbiter). tier structure (three levels), no pre-empting. tier structure (three levels), pre-empting.
100 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.9 interrupt servicing registers (continued) 10.1.9.2 syserr and clkerr output select register (continued) * when the arbitration control is disabled (0x00610 = 0000 0000), syserr or clkerr levels remain asserted until all the internal system (or clock) pending bits are cleared. table 85. syserr output select registers byte address name bit(s) mnemonic value function 0x00612 syserr output select 7:0 jsosr 0000 0000 0000 0001 0001 0000 0001 0001 syserr is active-high level* (default). syserr is active-low level*. syserr is active-high single pulse. syserr is active-low single pulse. 0x00616 syserr pulse width 7:0 jswsr llll llll syserr pulse-width value. 0x00613 clkerr output select 7:0 jcosr 0000 0000 0000 0001 0001 0000 0001 0001 clkerr is active-high level* (default). clkerr is active-low level*. clkerr is active-high single pulse. clkerr is active-low single pulse. 0x00617 clkerr pulse width 7:0 jcwsr llll llll clkerr pulse-width value.
agere systems inc. 101 data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.9 interrupt servicing registers (continued) 10.1.9.3 interrupt in-service registers the interrupt in-service registers provide a 16-bit interrupt vector, with unique encoding to indicate which of the 48 possible interrupts is currently in-service. table 86. interrupt in-service register byte address register name bit(s) mnemonic value function 0x006fc interrupt in-service low 7:0 reserved 0000 000 lower byte of in-service vector; returns zero. 0x006fd interrupt in-service high 7:0 jisor 0000 0000 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0001 0111 0010 0000 0010 0001 0010 0010 0010 0011 0010 0100 0010 0101 0010 0110 0010 0111 0100 0000 0100 0001 0100 0010 0100 0011 0100 0100 0100 0101 no interrupt in-service (default). fg0 interrupt in-service. fg1 interrupt in-service. fg2 interrupt in-service. fg3 interrupt in-service. fg4 interrupt in-service. fg5 interrupt in-service. fg6 interrupt in-service. fg7 interrupt in-service. gp0 interrupt in-service. gp1 interrupt in-service. gp2 interrupt in-service. gp3 interrupt in-service. gp4 interrupt in-service. gp5 interrupt in-service. gp6 interrupt in-service. gp7 interrupt in-service. sys0 interrupt in-service. sys1 interrupt in-service. sys2 interrupt in-service. sys3 interrupt in-service. sys4 interrupt in-service. sys5 interrupt in-service.
102 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.1 interrupt control registers (continued) 10.1.9 interrupt servicing registers (continued) 10.1.9.3 interrupt in-service registers (continued) the interrupt in-service registers provide a 16-bit interrupt vector, with unique encoding to indicate which of the 48 possible interrupts is currently in-service. table 86. interrupt in-service register (continued) byte address register name bit(s) mnemonic value function 0x006fd interrupt in-service high 7:0 0100 0110 0100 0111 0100 1000 0100 1001 0100 1010 0100 1011 0100 1100 0100 1101 0100 1110 0100 1111 1000 0000 1000 0001 1000 0010 1000 0011 1000 0100 1000 0101 1000 0110 1000 0111 1000 1000 1000 1001 1000 1010 1000 1011 1000 1100 1000 1101 1000 1110 1000 1111 sys6 interrupt in-service. sys7 interrupt in-service. sys8 interrupt in-service. sys9 interrupt in-service. sys10 interrupt in-service. sys11 interrupt in-service. sys12 interrupt in-service. sys13 interrupt in-service. sys14 interrupt in-service. sys15 interrupt in-service. clk0 interrupt in-service. clk1 interrupt in-service. clk2 interrupt in-service. clk3 interrupt in-service. clk4 interrupt in-service. clk5 interrupt in-service. clk6 interrupt in-service. clk7 interrupt in-service. clk8 interrupt in-service. clk9 interrupt in-service. clk10 interrupt in-service. clk11 interrupt in-service. clk12 interrupt in-service. clk13 interrupt in-service. clk14 interrupt in-service. clk15 interrupt in-service.
agere systems inc. 103 data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.2 error reporting and interrupt controller circuit operation t8110l errors are reported via two output signals, clkerr and syserr. these outputs are generated by an interrupt controller circuit; refer to figure 20. the interrupt control circuit accepts 48 interrupt inputs in all. the way in which these interrupts are arbitrated is selectable, and the means of reporting the interrupts out to the system is also selectable. 5-9425 (f) figure 20. interrupt controller fgio interrupt enable register syserr output select register edge/level sense generation syserr clkerr output select register edge/level sense generation arbitration control register logical or (unmasked clock sources) clkerr trigger clkerr arbitration clock errors clock interrupt pending registers 16 system interrupt pending registers gpio interrupt pending register fgio interrupt pending register clock interrupt enable registers system errors system interrupt enable registers 16 fg[7:0] gpio interrupt enable register gpio polarity, 8 8 16 16 interrupt in-service register 16 edge/level sense conversion gpio edge/level registers gp[7:0] edge/level sense conversion fgio polarity, fgio edge/level registers syserr trigger
104 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.2 error reporting and interrupt controller circuit operation (continued) 10.2.1 externally sourced interrupts via fg[7:0], gp[7:0] up to 16 of the 48 interrupt inputs are sourced external to the t8110l, via the fg[7:0] and gp[7:0] signals. each input is independently controlled via the interrupt control registers (refer to section 10.1.1 on page 90 and section 10.1.2 on page 92). any externally sourced interrupt may be presented as active-high level, active-low level, posi- tive edge, or negative edge sense. each external interrupt is maskable. any detected interrupt which is unmasked is held in an interrupt pending register, and presented to the arbitration circuit for servicing. 10.2.2 internally sourced system error interrupts another set of 16 of the 48 interrupt inputs are sourced internally via the system error register bits (0x00126?127). each of these inputs is independently controlled via the interrupt control registers (refer to section 10.1.3 on page 93). all internal system error bit interrupts are presented as active-high level sense. each system error bit interrupt is maskable. any detected interrupt which is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing. 10.2.3 internally sourced clock error interrupts another set of 16 of the 48 interrupt inputs are sourced internally via the latched clock error register bits (0x00122?123; refer to section 5.2.1 on page 40). each of these inputs is independently controlled via the inter- rupt control registers (refer to section 10.1.6 on page 96). all internal clock error bit interrupts are presented as active-high level sense. each clock error bit interrupt is maskable. any detected interrupt that is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing. 10.2.4 arbitration of pending interrupts the arbitration of the pending interrupts can be handled in one of four selectable modes: arbitration off, flat arbitra- tion, tier arbitration with pre-empting disabled, and tier arbitration with pre-empting enabled. interrupts are reported to the system via the syserr signal. 10.2.4.1 arbitration off this mode only allows the 16 internal system error register bits to generate interrupts, and no arbitration takes place. the trigger for the syserr output is simply a logical or of the internal system error register bits. all bits of the internal system error register must be cleared in order to rearm the syserr trigger in this mode. 10.2.4.2 flat arbitration the flat arbitration mode performs a round-robin arbitrations on all 48 interrupt sources. when a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, syserr is triggered, and that pending bit is cleared, removing it from the next round-robin arbitration cycle. the system must respond to the current in-service interrupt (refer to section 10.2.7 on page 105), after which the next arbitration cycle takes place. 10.2.4.3 tier arbitration the tier arbitration creates three prioritized groups as shown below: ! highest priority. the 16 internal latched clock error register bits. ! next highest priority. the 16 internal system error register bits. ! lowest priority. the 16 external fg[7:0] and gp[7:0] bits.
agere systems inc. 105 data sheet february 2004 ambassador t8110l h.100/h.110 switch 10 error reporting and interrupt control (continued) 10.2 error reporting and interrupt controller circuit operation (continued) 10.2.4 arbitration of pending interrupts (continued) 10.2.4.3 tier arbitration (continued) arbitration assigns interrupt servicing priority to the three groups. multiple pending interrupts within the same group are arbitrated round-robin. when a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, syserr is triggered, and that pending bit is cleared, removing it from the next arbitration cycle. 10.2.4.4 pre-empting disabled with pre-empting disabled, once a pending interrupt wins the arbitration and the in-service register is loaded with its corresponding interrupt vector, new incoming pending interrupts of higher priority must wait for the system to respond to the current in-service interrupt (refer to section 10.2.7 on page 105), at which time another arbitration cycle takes place. 10.2.4.5 pre-empting enabled with pre-empting enabled, an interrupt that is in-service (i.e., its interrupt vector is loaded in the in-service register and syserr has been triggered) can be overridden by new incoming pending interrupts of higher priority. the current in-service interrupt is pushed onto a stack for storage; the higher-priority interrupt vector is loaded into the in-service register and syserr is retriggered. once all interrupts of higher priority have been serviced by the sys- tem (refer to section 10.2.7 on page 105), the stack is popped and the original lower-priority interrupt is reissued. 10.2.5 clkerr output the clkerr output signal is used to indicate any internal clocking errors. the trigger for the clkerr output is simply a logical or of the internal latched clock error register bits. all bits of the internal clock error register must be cleared in order to rearm the clkerr trigger. the clkerr trigger induces a state machine to generate the clkerr signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or active- low single pulse. 10.2.6 syserr output the t8110l syserr output signal is used to report interrupts. internally, the arbitration circuit provides a syserr trigger, which induces a state machine to generate the syserr signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or active-low single pulse. 10.2.7 system handling of interrupts the t8110l interrupt controller presents an interrupt to the system by triggering the syserr output and providing a predefined interrupt vector value at the interrupt in-service register (isr). the system may acknowledge the interrupt in three ways as shown below: ! system reads the t8110l isr register. this allows the arbiter to advance, and if more pending interrupts are active, reloads the isr with the winner of the arbitration and retriggers syserr. ! system clears the t8110l isr register (via register 0x00100, soft reset; write 0x20 clears the isr). the arbiter advances, and if more pending interrupts are active, reloads the isr and retriggers syserr. ! system resets the interrupt controller (via register 0x00100, soft reset, write 0x10 clears the isr and all the pending interrupt registers). all pending interrupts are cleared, and the arbiter is reset.
106 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 11 test and diagnostics 11.1 diagnostics control registers the diagnostic control registers allow for various diagnostic modes (refer to section 11.2 on page 112). 11.1.1 fg testpoint enable register the fg testpoint enable register allows individual programming of fg[7:0] bits for either standard operation (as fg or fgio) or as testpoint outputs. fg testpoint select controls the mux selection for which testpoints are selected. refer to table 89 on page 107 for testpoint assignments for each fg bit. table 87. diagnostics control register map dword address (20 bits) register byte 3 byte 2 byte 1 byte 0 0x00140 diag3, gp testpoint select diag2, gp testpoint enable diag1, fg testpoint select diag0, fg testpoint enable 0x00144 diag7, external buffer retry timer diag6, miscellaneous diagnostics low diag5, state counter modes high diag4, state counter modes low 0x00148 diag11, sync-to- frame command off- set high diag10, sync-to- frame command off- set low diag9, interrupt controller syserr delay diag8, interrupt controller diagnostics table 88. fg testpoint enable registers byte address name bit(s) mnemonic value function 0x00140 diag0, fg testpoint enable 7 ft7eb 0 1 fg7 is standard fg or fgio bit (default). fg7 is a testpoint. 6 ft6eb 0 1 fg6 is standard fg or fgio bit (default). fg6 is a testpoint. 5 ft5eb 0 1 fg5 is standard fg or fgio bit (default). fg5 is a testpoint. 4 ft4eb 0 1 fg4 is standard fg or fgio bit (default). fg4 is a testpoint. 3 ft3eb 0 1 fg3 is standard fg or fgio bit (default). fg3 is a testpoint. 2 ft2eb 0 1 fg2 is standard fg or fgio bit (default). fg2 is a testpoint. 1 ft1eb 0 1 fg1 is standard fg or fgio bit (default). fg1 is a testpoint. 0 ft0eb 0 1 fg0 is standard fg or fgio bit (default). fg0 is a testpoint. 0x00141 diag1, fg testpoint select 7:0 ftpsr llll llll value for mux selection of testpoints out- put to fg[7:0]?see table 88 on page 106.
agere systems inc. 107 data sheet february 2004 ambassador t8110l h.100/h.110 switch 11 test and diagnostics (continued) 11.1 diagnostics control registers (continued) 11.1.1 fg testpoint enable register (continued) table 89. fg[7:0] internal testpoint assignments fg testpoint select value fg7 fg6 fg5 fg4 0000 0001 i_frame state_count[10:4] (actual time slot) 0000 0010 i_frame state_count_lookahead (lookahead time slot) 0000 0100 i_frame state_count_lookbehind (lookbehind time slot) 0000 1000 reserved reserved reserved reserved 0001 0000 reserved reserved reserved reserved 0010 0000 reserved 0100 0000 p_s_selector reserved ool threshold flag apll1 lock indicator 1000 0000 stalled snapping c clock enable b clock enable ? fg3 fg2 fg1 fg0 0000 0001 state_count[10:4] (actual time slot) 0000 0010 state_count_lookahead (lookahead time slot) 0000 0100 state_count_lookbehind (lookbehind time slot) 0000 1000 reserved reserved reserved reserved 0001 0000 reserved reserved reserved reserved 0010 0000 reserved 0100 0000 failsafe flag force-to-osc4 flag return from fs2 flag return from fs1 flag 1000 0000 a clock enable encoded abc states: 000 or 100 = diags 001 = a_only 010 = a_master 011 = a_error 101 = b_only 110 = b_master 111 = b_error
108 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 11 test and diagnostics (continued) 11.1 diagnostics control registers (continued) 11.1.2 gp testpoint enable register the gp testpoint enable register allows individual programming of gp[7:0] bits for either standard operation (as gpio) or as testpoint outputs. gp testpoint select controls the mux selection for which testpoints are selected. refer to table 91 on page 109 for testpoint assignments for each gp bit. table 90. testpoint enable registers byte address name bit(s) mnemonic value function 0x00142 diag2, gp testpoint enable 7gt7eb 0 1 gp7 is standard gpio bit (default). gp7 is a testpoint. 6gt6eb 0 1 gp6 is standard gpio bit (default). gp6 is a testpoint. 5gt5eb 0 1 gp5 is standard gpio bit (default). gp5 is a testpoint. 4gt4eb 0 1 gp4 is standard gpio bit (default). gp4 is a testpoint. 3gt3eb 0 1 gp3 is standard gpio bit (default). gp3 is a testpoint. 2gt2eb 0 1 gp2 is standard gpio bit (default). gp2 is a testpoint. 1gt1eb 0 1 gp1 is standard gpio bit (default). gp1 is a testpoint. 0gt0eb 0 1 gp0 is standard gpio bit (default). gp0 is a testpoint. 0x00143 diag3, gp testpoint select 7:0 gtpsr llll llll value for mux selection of testpoints output to gp[7:0]?see table 90 on page 108.
agere systems inc. 109 data sheet february 2004 ambassador t8110l h.100/h.110 switch 11 test and diagnostics (continued) 11.1 diagnostics control registers (continued) 11.1.2 gp testpoint enable register (continued) table 91. gp[7:0] internal testpoint assignments gp testpoint select value gp7 gp6 gp5 gp4 0000 0001 byteref_16 byteref_8 byteref_4 byteref_2 0000 0010 i_frame reserved cp8 read cp8 write 0000 0100 reserved 0000 1000 reserved reserved reserved reserved 0001 0000 reserved reserved reserved reserved 0010 0000 dpll2 lock dpll1 lock reserved 0100 0000 p_s_selector fallback encoded states: 000 = primary 001 = to_primary 010 = secondary 011 = to_secondary 100 = fs1 101 = fs2 110 = [reserved] 111 = initial 1000 0000 stalled snapping reserved reserved ?gp3 gp2 gp1 gp0 0000 0001 state_count[3:0] (stream) 0000 0010 cp4 read cp4 write cp2 read cp2 write 0000 0100 reserved 0000 1000 reserved reserved reserved reserved 0001 0000 reserved reserved reserved reserved 0010 0000 reserved 0100 0000 fallback flag go_clocks indicator clear_fallback indicator force_fallback indicator 1000 0000 phase alignment frame event apll1 feedback, 8 mhz tap apll1 feedback, 4 mhz tap apll1 feedback, 2 mhz tap
110 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 11 test and diagnostics (continued) 11.1 diagnostics control registers (continued) 11.1.3 state counter modes registers the state counter modes registers control state counter diagnostics, including the breaking of state counter carry chains, using /fr_comp as the internal frame reference, and allowing the state counter to roll over early via a modulo function. for more details, refer to section 11.2 on page 112. 11.1.4 miscellaneous diagnostics low register the miscellaneous diagnostics low register: bits 2 and 1 allow direct reset of the apll2 and apll1 feedback divid- ers. bit 0 controls the tst input of the power-on reset cell. table 92. state counter modes registers byte address name bit(s) mnemonic value function 0x00144 diag4, state counter modes low 7:0 scmlr llll llll lower 8 bits of state counter modulo load value. 0x00145 diag5, state counter modes high 7:6 reserved 00 nop (default). 5scmsb 0 1 normal carry chain operation (default). break state counter carry chains. 4frmsb 0 1 normal internal frame operation (default). use /fr_comp as internal frame. 3sclsb 0 1 normal counting (default). state counter modulo counting. 2:0 sculp lll upper 3 bits of state counter modulo load value. table 93. miscellaneous diagnostics low register byte address name bit(s) mnemonic value function 0x00146 diag6, miscellaneous diagnostics low 7:3 reserved 00 nop (default). 2 fb2sb 0 1 apll2 feedback divider reset inactive (default). apll2 feedback divider reset active. 1 fb1sb 0 1 apll1 feedback divider reset inactive (default). apll1 feedback divider reset active. 0 reserved ? ?
agere systems inc. 111 data sheet february 2004 ambassador t8110l h.100/h.110 switch 11 test and diagnostics (continued) 11.1 diagnostics control registers (continued) 11.1.5 miscellaneous diagnostic registers table 94. miscellaneous diagnostic registers byte address name bit(s) mnemonic value function 0x00147 diag7 7:0 reserved ? nop. 0x00148 diag8, interrupt controller diagnostic 7:6 icdsp 00 01 interrupt controller, normal mode (default). interrupt controller, diag mode. 5:4 icklp ll diag mode, force clk[1:0] errors. 3:2 isylp ll diag mode, force sys[1:0] errors. 1:0 iexlp ll diag mode, force ext[8, 0] errors. 0x00149 diag9, interrupt control- ler deassertion delay 7:0 iaslr llll llll programmable delay to control the deas- sertion time of syserr. 0x0014a diag10, sync-to-frame command delay (lower) 7:0 cfllr llll llll low byte of 12-bit offset value for sync-to- frame clock commands (go_clocks, clear_fallback, force_fallback). 0x0014b diag11, sync-to-frame command delay (upper) 7:4 cfsen 0000 0001 disable delay mode (default). enable delay mode. 3:0 cfhln llll upper 4 bits of 12-bit offset value for sync-to-frame clock commands (go_clocks, clear_fallback, force_fallback).
112 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 11 test and diagnostics (continued) 11.2 diagnostic circuit operation the t8110l internal diagnostic modes are intended primarily for chip manufacturing test. the diagnostic functions include the following: ! diag0?3, observability of internal testpoints via fg(7:0), gp(7:0): ? internal testpoints are brought to chip i/o at fg and gp signals. refer to table 89 on page 107 and table 91 on page 109 for testpoint assignment. ! diag4?5, internal state counter diagnostic modes: ? break counter carry chains?this is used in conjunction with monitoring of the state counter bits at fg and gp, and breaks the 11-bit state counter into three separate pieces (bits [10:8], [7:4] and [3:0]). ? shorten frame operation?the internally generated 8 khz frame is bypassed in favor of the /fr_comp input. the /fr_comp input still denotes the frame center and may be presented at a higher frequency than 8 khz. this is used in conjunction with the state counter modulo function, which when properly programmed allows the internal state counter to roll over coincident with the /fr_comp frame center. ! diag6, forced reset of analog apll1 feedback dividers: ? the apll1 feedback dividers are typically not reset. this diagnostic mode allows each feedback divider to be held in a reset state. ! diag7, reserved. ! diag8, interrupt controller diagnostics: ? when the diagnostic mode is enabled (diag8 register, bits 7:6 = 01), then bits 5:4 override the clk error[1:0] inputs, bits [3:2] override the sys error[1:0] inputs, bit 1 overrides the gp[0] input, and bit 0 overrides the fg[0] input to the interrupt controller. this allows for direct manipulation to set/clear a portion of interrupt bits from each tier group. please see section 10.2 on page 103 for more details. ! diag9, interrupt controller deassertion delay: ? allows a programmable deassertion time for the syserr signal in between back-to-back interrupts. ! diag10?11, sync-to-frame command delay: ? allows a programmable delay time from the frame boundary for execution of the sync-to-frame clock com- mands, go_clocks, clear_fallback, force_fallback.
agere systems inc. 113 data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control 12.1 programming interface programming the t8110l for time-slot switching requires specific access cycles to the connection memory regions. access to other regions (data memory or registers) is made through a standard direct access via the inter- face. 12.1.1 connection memory programming because the microprocessor interface only allows word or byte accesses, multiple write accesses must occur. for byte access, there are a total of three byte-wide holding registers. for word access, there is one word-wide holding register. the user must load the holding registers with the proper information first, and then write to the upper byte (or upper word) to actually move data into the connection memory; refer to table 95. the connection memory is divided into four 2k regions, each of which handles up to 128 time slots worth of con- nectivity for each of 16 serial data streams. the regions include h1x0 even streams (ct_d[30, 28, . . . 0]), h1x0 odd streams (ct_d[31, 29, . . . 1]), local low streams (l_d[15:0]), and local high streams (l_d[31:16]). the con- nection memory locations are addressed relative to time slot and stream. connection memory commands are as follows: ! reset page resets any (up to all four) connection memory region (see figure 21 on page 114). address bit 15 determines whether or not it's a reset page command. the reset page command relies on a valid internal chip clock and loops through all addresses within the connection memory region, resetting the valid bit field. the reset page command is presented as either two microprocessor word writes, or four microprocessor byte writes, see table 95. ! make/break/query, telephony connection (see figure 22 on page 114). the make and break commands are presented as multiple microprocessor write cycles. the query command is presented as multiple microprocessor read cycles; refer to table 95. note: data byte n required information is shown in figure 22. table 95. microprocessor programming, connection memory access word/byte (wb_sel) a[1:0] d[15:8] d[7:0] access description byte 00 x data byte 0 write data byte 0 to a holding register, or read data byte 0 information. byte 01 x data byte 1 write data byte 1 to a holding register, or read data byte 1 information. byte 10 x data byte 2 write data byte 2 to a holding register, or read data byte 2 information. byte 11 x data byte 3 write data byte 3 plus the holding register data to con- nection memory, or read data byte 3 information. word 0x data byte 1 data byte 0 write data bytes 1 and 0 to a holding register, or read data bytes 1 and 0 information. word 1x data byte 3 data byte 2 write data bytes 3 and 2 plus the holding register data to connection memory, or read data bytes 3 and 2 infor- mation.
114 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.1 programming interface (continued) 12.1.1 connection memory programming (continued) figure 21. microprocessor programming?reset page command 5-9632 (f) figure 22. microprocessor programming?make/break/query telephony connections 19:16 0100 15 1 14:0 000000000000000 a[19:0] 0 = no action 1 = reset h-bus odd region 0 = no action 1 = reset h-bus even region 0 = no action 1 = reset local hi region 0 = no action 1 = reset local lo region rho rhe rlh rll 7:1 0000000 data byte 1 bit 0 7:1 0000000 data byte 0 bit 0 7:1 0000000 data byte 3 bit 0 7:1 0000000 data byte 2 bit 0 a[19:0] 19:16 0100 15 0 14:8 time slot 7 6:2 stream 1:0 7:0 tag (lower bits) 76:0 subrate 7:4 0000 3:0 0 data byte 0 h-bus/local select: 0 = local streams 1 = h.1x0 streams hls word/byte address lsbits tag (upper bits) data byte 2 0 1 2 3 6:4 7 000 0 data byte 1 data byte 3 mbs 0 = make connection 1 = break connection 0 = write to data memory 1 = read from data memory 0 = pattern mode disabled 1 = pattern mode enabled 0 = use current frame 1 = use next frame rws vfc pme
agere systems inc. 115 data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.2 switching operation the basic building block of switching is one-half simplex connections loaded into the connection memory. each connection memory location controls data flow, either from a serial stream input to a location in data memory, or from data memory to a serial stream output. a typical telephony simplex switch connection would use one from and one to connection, each using the same data memory location. 12.2.1 memory architecture and configuration 12.2.1.1 connection memory the t8110l connection memory consists of 8192 locations, one location for each of the possible stream/time-slot combinations, to provide a full nonblocking switch for up to 128 time slots on 32 h1x0 streams (ct_d[31:0]) and 32 local streams (l_d[31:0]). connection memory is physically addressed by time slot (7 bits), h1x0/local select (1 bit), and stream (5 bits). the 8192 locations are divided into four pages of 2048, with each page dedicated to a set of 16 serial streams as follows: ! h1x0 even streams (ct_d[30, 28, . . . 0]) ! h1x0 odd streams (ct_d[31, 29, . . . 1]) ! local high streams (l_d[31:16]) ! local low streams (l_d[15:0]) each of these connection memory pages are initialized at reset (valid bit entries are reset to invalid). additionally, each page may be initialized individually via software command, reset page (refer to figure 21 on page 114). connection memory locations contain the following control information: ! valid bit indicates that a valid switch connection exists for this stream/time slot. ! rws indicates whether the connection is from (from serial stream to data memory) or to (from data memory to serial stream). ! vfc (virtual framing control) controls which data page is used in double-buffer scenarios. note: there are two data memory configurations that allow double-buffering of the data, in order to create con- stant frame delay connections. refer to section 12.2.1.2 on page 116 and section 12.2.2.1 on page 117. ! pme indicates a pattern mode connection. ! tag is the data memory location used for this one-half simplex switch connection (or the data pattern sent to serial output for pattern mode connections). ! subrate information is subrate switching control (bitswap).
116 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.2 switching operation (continued) 12.2.1 memory architecture and configuration (continued) 12.2.1.2 data memory the t8110l data memory is 4096 bytes, which can be programmatically configured in three ways, via the data memory mode select register (0x00105; refer to section 5.1.3 on page 32). 5-9638 (f) figure 23. t8110l data memory map and configurations tel data memory modes tel tel tel tel tel 0x20000 0x20fff 0x20000 0x207ff 0x20800 0x20bff 0x20000 0x207ff (set by control register 0x00105) 4k single- buffered switch 2k single buffered + 1k double buffered 2k double- buffered switch 0x2ffff (reserved) 0x21000 0x20fff 0x20000 4k utilized total addressed space is 64k data memory addressing
agere systems inc. 117 data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.2 switching operation (continued) 12.2.2 standard switching standard telephony switching is achieved by loading control fields into the connection memory for one-half simplex connections (refer to figure 22 on page 114, and section 12.2.1.1 on page 115). 12.2.2.1 constant delay and minimum delay connections the vfc control bit in connection memory determines which of two data pages is accessed, when the data mem- ory is configured to double-buffering for telephony connections (refer to figure 23). this bit always affects to con- nections (read the data memory, send it out to a serial stream output) in a double-buffer configuration. this bit can control a from connection in a double-buffer configuration, only if it is a subrate connection; otherwise, the vfc bit has no bearing on from connections. the double-buffering configuration creates two data pages. during a particular frame (125 s time boundary, parti- tioned into time slots), one page is the active page, the other is the inactive page. the active/inactive page status toggles at every frame boundary. for all from connections (except for subrate connections), incoming serial data is always written to the active page. for all to connections, the vfc control bit indicates whether to read from the active or inactive page. manipulation of this bit affects the latency between the incoming from data and the outgo- ing to data. this latency defines whether or not a connection is constant delay or minimum delay. please see appendix a on page 139 for more details on constant and minimum delay connections. 12.2.2.2 pattern mode the pme control bit in connection memory affects only to connections. instead of reading a value out of the data memory for subsequent output to a serial stream, the lower 8 bits of the tag field provide a byte pattern for the serial output. 12.2.2.3 subrate the subrate control bit field in connection memory is used only by from connections and controls how individual bits or groups of bits of an incoming serial byte are shuffled prior to writing them to the data memory, in order to achieve subrate switching.
118 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.2 switching operation (continued) 12.2.2 standard switching (continued) 12.2.2.1 subrate (continued) subrate switching overview traditional byte-oriented tdm data switching provides 8 bits of data per time slot, or channel, regardless of the tdm stream bit rate. a particular channel occurs once every 8 khz frame, and there are 8k frames per second. this allows for a channel data propagation rate of (8 bits/frame * 8k frames/s = 64 kbits/s). refer to figure 24 and table 97. figure 24. tdm data stream bit rates subrate refers to switching fractional portions of the byte-oriented tdm data streams. the t8110l allows the 8 bits of a byte-oriented channel to be broken into multiple channels of fewer bits, either two 4-bit channels, four 2-bit channels, or eight 1-bit channels. this lowers the data propagation rate per channel, but increases the overall channel capacity for a given time slot. refer to table 96 and table 97. notes: bit subrate = 8 channels per time slot, 1 bit per channel. di-bit = 4 channels per time slot, 2 bits per channel. nibble subrate = 2 channels per time slot, 4 bits per channel. byte (no subrate) = 1 channel per time slot, 8 bits per channel. table 96. tdm data stream bit76543210 di-bit 7:6 5:4 3:2 1:0 nibble 7:4 3:0 byte 7:0 0 1 2 3 4 5 6 7 0 1 2 3 0 1 124 125 126 127 62 63 31 one frame (8 khz) tdm stream bit rate = 8mb/s: each stream has 128 timeslots (channels) per frame tdm stream bit rate = 4 mbits/s: each stream has 64 time slots (channels) per frame tdm stream bit rate = 2 mbits/s: each stream has 32 time slots (channels) per frame each channel contains one 8-bit byte, regardless of the tdm data stream bit rate 8 mbits/s 4 mbits/s 2 mbits/s tdm stream bit rate = 8 mbits/s: each stream has 128 time slots (channels) per frame one time slot (or channel)
agere systems inc. 119 data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.2 switching operation (continued) 12.2.2 standard switching (continued) 12.2.2.1 subrate (continued) subrate switching overview (continued) subrate switching using t8110l the h1x0 bus and the local stream bus are based on byte-oriented tdm data streams?data is always switched as whole bytes. the subrate data must be packed into these bytes prior to switching (refer to sections and ). the data bytes are not necessarily constrained to using fully packed bytes?any portion of a byte may be used. sub- rate switching using t8110l requires the following: ! overall subrate enable mode is activated (register 0x00105, data memory mode select bit 7 is set; see section 5.1.3 on page 32). ! the subrate field of the connection memory entry for that switch connection is set up. this field contains 7 bits which control the type of subrate (i.e., bit, di-bit, nibble, or byte), and the data bit shuffling within the tdm byte data, from and to (refer to figure 22 on page 114, and table 98). ! the vfc connection memory bit for cases where a double-buffering configuration is set up in the data memory (refer to figure 22, and sections 12.2.1.2, 12.2.2.1). in order to program a subrate simplex connection, the subrate field is only required for the from half of that con- nection. incoming serial byte data has its bit positions rearranged based on the subrate field contents prior to being written into the data memory. for double-buffered data memory configurations, the vfc bit controls which of two data pages the rearranged byte is written to. the to half of a subrate simplex connection simply outputs the entire byte found at the data memory location used for that connection, and its connection memory subrate field is ignored. table 97. subrate switching, data propagation rate vs. channel capacity subrate type bits per channel channel data propagation rate (bits/frame x 8k frames/s) channel capacity (relative to byte switching) bit 1 8 kbits/s 8x di-bit 2 16 kbits/s 4x nibble 4 32 kbits/s 2x byte (no subrate) 8 64 kbits/s 1x
120 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.2 switching operation (continued) 12.2.2 standard switching (continued) 12.2.2.1 subrate (continued) subrate switching using t8110l (continued) subrate packing of outgoing bytes the output from subrate connections is always an entire byte so that it does not violate the h.100 or h.110 specifi- cations. the output byte is composed of smaller, i.e., subrate pieces. the process of combining the incoming pieces into a whole byte suitable for output is called packing . in the t8110l (and other subrate-capable ambassa- dor devices), packing is accomplished by making several from connections for each single to connection. for example, in figure 25, four from connections (of different stream/time-slot origins), all di-bits, are used to construct a byte that will be output as defined by the to connection. the outgoing to half of a simplex connection reads an entire byte from a data memory location. the packing of separate incoming subrate pieces into this byte is achieved by setting up multiple from one-half simplex connec- tions for one to one-half simplex connection, all using the same data memory location. an example is illustrated in figure 25. this example shows the packing of four separate incoming di-bits from four different channels into one outgoing byte on one channel. note: please note the limitation that multiple di-bits from the same time slot cannot be switched simultaneously. this would require the byte of that time slot to be unpacked first, which is discussed in section on page 122. table 98. subrate switching, connection memory programming setup subrate type subrate connection memory bit field (6:0) 65 4 3 21 0 bit 1 000 = from bit 0 001 = from bit 1 010 = from bit 2 011 = from bit 3 100 = from bit 4 101 = from bit 5 110 = from bit 6 111 = from bit 7 000 = to bit 0 001 = to bit 1 010 = to bit 2 011 = to bit 3 100 = to bit 4 101 = to bit 5 110 = to bit 6 111 = to bit 7 subrate connection memory bit field (6:0) 65 4 3 21 0 di-bit 01 00 = from bits[1:0] 01 = from bits[3:2] 10 = from bits [5:4] 11 = from bits[7:6] reserved 00 = to bits[1:0] 01 = to bits[3:2] 10 = to bits[5:4] 11 = to bits[7:6] subrate type subrate connection memory bit field (6:0) 65 4 3 21 0 nibble 001 0 = from bits[3:0] 1 = from bits[7:4] reserved 0 = to bits[3:0] 1 = to bits[7:4] subrate connection memory bit field (6:0) 65 4 3 21 0 byte 000 reserved
agere systems inc. 121 data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.2 switching operation (continued) 12.2.2 standard switching (continued) 12.2.2.1 subrate (continued) subrate packing of outgoing bytes (continued) notes: connectivity is as follows: ! from stream a, time slot n, bits[1:0] to stream e, time slot n + 10, bits[7:6]. ! from stream b, time slot n + 1, bits[1:0] to stream e, time slot n + 10, bits[3:2]. ! from stream c, time slot n + 2, bits[3:2] to stream e, time slot n + 10, bits[1:0]. ! from stream d, time slot n + 3, bits[5:4] to stream e, time slot n + 10, bits[5:4]. required connection memory programming is as follows: five 1/2 simplex connections are required to pack four incoming di-bits into an outgoing byte. ! from stream a, time slot n. connection memory subrate field = 0100x11. ! from stream b, time slot n + 1. connection memory subrate field = 0100x01. ! from stream c, time slot n + 2. connection memory subrate field = 0101x00. ! from stream d, time slot n + 3. connection memory subrate field = 0110x10. ! to stream e, time slot n + 10. connection memory subrate field is don't care. figure 25. subrate switching example, byte packing frame (8 khz) time slot stream a, di-bit channels in stream b, di-bit channels in stream c, di-bit channels in bit postitions of di-bits within the data byte stream d, di-bit channels in stream e, di-bit channels out n n + 1 n + 2 n + 3 t i m e s l o t n + 10 7: 6 5: 4 3: 2 1: 0 a 1 a 2 a 3 a 4 b 1 b 2 b 3 b 4 a 4 d 2 b 4 c 3 c 1 c 2 c 3 c 4 d 1 d 2 d 3 d 4 7: 6 5: 4 3: 2 1: 0 7: 6 5: 4 3: 2 1: 0 7: 6 5: 4 3: 2 1: 0 7: 6 5: 4 3: 2 1: 0
122 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.2 switching operation (continued) 12.2.2 standard switching (continued) 12.2.2.1 subrate (continued) subrate unpacking of incoming bytes because the h1x0 bus and the local stream bus are based on byte-oriented tdm data streams, and the t8110l architecture is geared towards standard byte switching, it is not possible to simultaneously switch subrate portions of a single byte to different places. this limitation is overcome by application. to gain access to each subrate piece contained in one incoming byte, that byte must be broadcast onto additional channels, one channel for each sub- rate piece required. the means of broadcasting is up to the application?either the source device of the packed subrate byte can broadcast it, or the device receiving that byte can broadcast it over unused channels and loop the broadcast bytes back in. the example from figure 25 is extended in figure 26. this example shows the unpacking of the packed byte created in figure 25, output to four different channels.
agere systems inc. 123 data sheet february 2004 ambassador t8110l h.100/h.110 switch 12 connection control (continued) 12.2 switching operation (continued) 12.2.2 standard switching (continued) 12.2.2.1 subrate (continued) subrate unpacking of incoming bytes (continued) notes: connectivity is as follows: from stream e, time slot n + 3, bits[1:0] to stream j, time slot n + 8, bits[7:6]. from stream f, time slot n + 5, bits[3:2] to stream i, time slot n + 8, bits[5:4]. from stream f, time slot n + 6, bits[5:4] to stream h, time slot n + 8, bits[1:0]. from stream f, time slot n + 7, bits[7:6] to stream g, time slot n + 8, bits[7:6]. required connection memory programming is as follows: eight 1/2 simplex connections are required to unpack one incoming byte to four separate outgoing di-bits. from stream e, time slot n + 3. connection memory subrate field = 0100x11. from stream f, time slot n + 5. connection memory subrate field = 0101x10. from stream f, time slot n + 6. connection memory subrate field = 0110x00. from stream f, time slot n + 7. connection memory subrate field = 0111x11. to stream g, time slot n + 8. connection memory subrate field is don't care. to stream h, time slot n + 8. connection memory subrate field is don't care. to stream i, time slot n + 8. connection memory subrate field is don't care. to stream j, time slot n + 8. connection memory subrate field is don't care. figure 26. subrate switching example, byte unpacking n + 3 n + 4 n + 5 n + 6 frame (8 khz) time slot time slot bit positions of di-bits within the data byte n + 7 7: 6 5: 4 3: 2 1: 0 stream e, di-bit channels in a 4 d 2 b 4 c 3 7: 6 5: 4 3: 2 1: 0 7: 6 5: 4 3: 2 1: 0 7: 6 5: 4 3: 2 1: 0 7: 6 5: 4 3: 2 1: 0 n + 8 a 4 d 2 b 4 c 3 a 4 d 2 b 4 c 3 a 4 d 2 b 4 c 3 stream f, di-bit channels in (broadcasts of the original input) stream g, di-bit channels out stream h, di-bit channels out stream i, di-bit channels out stream j, di-bit channels out a 4 x x x x x x d 2 x b 4 x x c 3 x x x broadcasted incoming byte 7: 6 5: 4 3: 2 1: 0
124 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics 13.1 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage; the table below shows abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. 13.1.1 handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. agere employs a human-body model (hbm) and a charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the model. no industry-wide standard has been adopted for cdm. however, a standard hbm (resistance = 1500 w, capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the t8110l has a hbm esd threshold voltage rating of 1500 v minimum. 13.2 crystal specifications 13.2.1 xtal1 crystal the t8110l requires a 16.384 mhz clock source derived from an oscillator or a crystal. if a crystal is used it has to be a 16.384 mhz crystal and must be connected between the xtal1_in and the xtal1_out pins. external 24 pf, 5% capacitors must be connected from xtal1_in and xtal1_out to vss, as shown in the diagram below. the 32 ppm tolerance is the suggested value if the oscillator is used as the clocking source while mastering the bus. otherwise, a crystal with a lesser tolerance can be used. the crystal specifications are shown below. table 99. absolute maximum ratings parameter symbol min max unit supply voltage v dd ?4.2v xtal1_in, xtal2_in, xtal1_out, xtal2_out pins ? v ss v dd v voltage applied to i/o pins ? v ss ? 0.3 v dd 5.5 v operating temperature ? ?40 85 c storage temperature t stg ?55 125 c table 100. xtal1 specifications parameter value frequency 16.384 mhz oscillation mode fundamental, parallel resonance effective series resistance 50 ? maximum load capacitance 18 pf shunt capacitance 7 pf maximum frequency tolerance and stability 32 ppm 5-6390f(c) v ss 24 pf 24 pf 1 m ? 16.384 mh z t8110l xtal1_in xtal1_out crystal
agere systems inc. 125 data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics (continued) 13.2 crystal specifications (continued) 13.2.1 xtal1 crystal (continued) if an oscillator is used (see section 6.4.4 on page 61), the signal has to be connected to the xtal1_in pin. xtal1_out must be left unconnected in this configuration. xtal1_in and xtal1_out are not 5 v tolerant. the oscillator must meet the requirements shown below. 13.2.2 xtal2 crystal xtal2 is an optional crystal oscillator input. if a crystal is used, it has to be a 6.176 mhz or a 12.352 mhz crystal and must be connected between the xtal2_in and the xtal2_out pins, as shown in the diagram below. exter- nal 24 pf, 5% capacitors must be connected from xtal2_in and xtal2_out to vss. the 32 ppm tolerance is the suggested value if the oscillator is used as the clocking source while mastering the bus. otherwise, a crystal with a lesser tolerance can be used (see table 121). if xtal2 is not used, xtal2_in should be tied to v dd and xtal2_out should be left unconnected. * 120 ? maximum for 6.176 mhz crystal. ? 24 pf for 6.176 mhz crystal also. ? 18 pf for 6.176 mhz crystal also. if an oscillator is used (see section 6.5.1 on page 63), the signal has to be connected to the xtal2_in pin. xtal2_out must be left unconnected in this configuration. xtal2_in and xtal2_out are not 5 v tolerant. the oscillator must meet the requirements shown below. table 101. 16.384 mhz oscillator requirements parameter value frequency 16.384 mhz maximum rise or fall time 10 ns, 10%?90% v dd minimum pulse width low high 20 ns 20 ns table 102. xtal2 specifications parameter value frequency 12.352 mhz oscillation mode fundamental, parallel resonance effective series resistance 75* ? maximum load capacitance 18 ? pf shunt capacitance 7 pf maximum frequency tolerance and stability 32 ppm 5-6390d table 103. 6.176 mhz/12.352 mhz oscillator requirements parameter value value frequency 6.176 mhz 12.352 mhz maximum rise or fall time 10 ns, 10%?90% v dd 10 ns, 10%?90% v dd minimum pulse width low high low high 54 ns 54 ns 27 ns 27 ns v ss 24 pf ? 24 pf ? 1 m ? t8110l xtal2_in xtal2_out 12.352 mhz crystal
126 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics (continued) 13.2 crystal specifications (continued) 13.2.3 reset pulse 13.3 thermal parameters (definitions and values) system and circuit board level performance depends not only on device electrical characteristics, but also on device thermal characteristics. the thermal characteristics frequently determine the limits of circuit board or system perfor- mance, and they can be a major cost adder or cost avoidance factor. when the die temperature is kept below 125 c, temperature activated failure mechanisms are minimized. the thermal parameters that agere provides for its packages help the chip and system designer choose the best package for their applications, including allowing the system designer to thermally design and integrate their systems. it should be noted that all the parameters listed below are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. ja ?junction to air thermal resistance ja is a number used to express the thermal performance of a part under jedec standard natural convection con- ditions. ja is calculated using the following formula: ja = (t j ? t amb )/p; where p = power jma ?junction to moving air thermal resistance jma is effectively identical to ja but represents performance of a part mounted on a jedec four layer board inside a wind tunnel with forced air convection. jma is reported at airflows of 200 lft./min and 500 lft./min, which roughly correspond to 1 m/s and 2.5 m/s (respectively). jma is calculated using the following formula: jma = (t j ? t amb )/p jc ?junction to case thermal resistance jc is the thermal resistance from junction to the top of the case. this number is determined by forcing nearly 100% of the heat generated in the die out the top of the package by lowering the top case temperature. this is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. jc is calculated using the following formula: jc = (t j ? t c )/p table 104. reset pulse parameter min max unit reset# minimum pulse width 61 ? ns
agere systems inc. 127 data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics (continued) 13.3 thermal parameters (definitions and values) (continued) jb ?junction to board thermal resistance jb is the thermal resistance from junction to board. this number is determined by forcing the heat generated in the die out of the package through the leads or balls by lowering the board temperature and insulating the package top. this is done using a special fixture, which keeps the board in contact with a water chilled copper slug around the perimeter of the package while insulating the package top. jb is calculated using the following formula: jb = (t j ? t b )/p jt jt correlates the junction temperature to the case temperature. it is generally used by the customer to infer the junction temperature while the part is operating in their system. it is not considered a true thermal resistance. jt is calculated using the following formula: jt = (t j ? t c )/p 13.4 reliability product reliability can be calculated as the probability that the product will perform under normal operating condi- tions for a set period of time. factors influencing the reliability of a product cover a range of variables, including de- sign and manufacturing. the failure rate of a product is given as the number of units failing per unit time. this failure rate is known as fit, which is as follows: 1 fit = 1 failure/1x10e 9 hours. another unit used for failure rate is known as mtbf, which is 1/fit. many assumptions are made when calculating the failure rate for a product, such as the average junction temperature and activation energy. the assumptions made for calculating fit and mtbf are shown in table 106: table 105. thermal parameter values parameter temperature c/watt ja 22 jma (1 m/s) 19 jma (2.5 m/s) 17.5 jc 20 jb tbd jt 1.0 table 106. reliability data junction temperature fit (per 10e 9 device hours mtbf activation energy 55 c 10 1.0e 8 hours .7ev
128 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics (continued) 13.5 dc electrical characteristics 13.5.1 electrical drive specifications, ct_c8 and /ct_frame v dd = 3.3 v and v ss = 0.0 v, unless otherwise specified. pci-compliant data line i/o cells are used for the ct bus data lines. (see pci specification , rev. 2.2, chapter 4.) /c16, /c4, c2, sclk, /sclkx2, and /fr_comp all use the same driver/receiver pairs as those specified for the ct_c8 and /ct_frame signals, though this is not explicitly stated as a part of the h.1x0 specification. table 107. electrical drive specifications, ct_c8 and /ct_frame parameter symbol condition min max unit output high voltage v oh i out = ?24 ma 2.4 3.3 v output low voltage v ol i out = 24 ma ?0.25 0.4 v positive-going threshold vt+ ? 1.2 2.0 v negative-going threshold vt? ? 0.6 1.6 v hysteresis (vt+?vt?) v hys ?0.4?v input pin capacitance c in ? ? 10 pf
agere systems inc. 129 data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics (continued) 13.5 dc electrical characteristics (continued) 13.5.2 all other pins v dd = 3.3 v and vss = 0.0 v, unless otherwise specified. 13.6 h-bus timing 13.6.1 timing diagrams 5-6119f figure 27. clock alignment table 108. dc electrical characteristics, all other pins parameter symbol condition min typ max unit supply current i dd 2000 h-bus/l-bus connections ? 300 ? ma supply voltage v dd ? 3.0 ? 3.6 v input high voltage v ih ?2.0??v input low voltage v il ???0.8v input current i i ???1 a input capacitance (input only) c i ???5pf input capacitance (i/o pins) c io ???10pf leakage current (3-state) i leak ???10 a input clamp voltage v c ????1.0v output high voltage v oh i = 8 ma 2.4 ? ? v output low voltage v ol i = 8 ma ? ? 0.4 v output short-circuit current i os v oh tied to gnd ? ? 100 ma /ct_frame (a/b) ct_c8 (a/b) /fr_comp /c16 c2 /c4 sclk sclk /sclkx2 /sclkx2 sclk (2.048 mhz) (2.048 mhz mode) (4.096 mhz mode) (4.096 mhz mode) (8.192 mhz mode) (8.192 mhz mode) /sclkx2 frame boundary
130 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics (continued) 13.6 h-bus timing (continued) 13.6.1 timing diagrams (continued) note: bit 1 is the msb and bit 8 is the lsb. msb is always transmitted first in all transfers. 5-6120f figure 28. frame timing diagram 5-6122f figure 29. detailed clock skew timing diagram 13.7 ac electrical characteristics 13.7.1 skew timing, h-bus * test load?50 pf. ? assumes a and b masters in adjacent slots. ? when static skew is 10 ns and in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum skew of 30 ns will occur during that clock cycle. meeting the skew requirements in table 109 and the requirements of section 15.5 h-bus timing on page 129 could require the plls generating ct_c8 to have different time constants when acting as primary and secondary clock masters. table 109. skew timing, h-bus symbol parameter min typical max unit tskc8 maximum skew between ct_c8_a and ct_c8_b* ?? ??10, ns tskcomp maximum skew between ct_c8_a and any compatibility clock* ? ? 5 ns ? maximum skew between ct_c8_a and l_scx clock* ? ? 2 ns 812345678 123456781 127 0 /ct_frame ct_c8 ct_dx time slot 125 s frame boundary vt+ vt+ ct_c8_a ct_c8_b tskc8 vt+ vt+ ct_c8_a compatibility tskcomp clocks vt? tskcomp
agere systems inc. 131 data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics (continued) 13.7 ac electrical characteristics (continued) 13.7.1 skew timing, h-bus (continued) * worst-case loading of 50 pf on all outputs. 13.8 hot swap the t8110l has features which assist in h.110 hot swap applications. all h.110 bus signals are put in high imped- ance (3-state and/or input) during the early power phase of board insertion/removal. the ectf h.110 specification requires that all ct data lines and ct_netref clocks have 0.7 v applied through 18 k ? resistors before plugging into and releasing from the h.110 bus. a feature on the t8110l incorporates all 34 18 k ? precharge resistors inter- nally (32 for the ct data signals, 2 for netrefs). these resistors accept 0.7 v directly through the vpre- charge input. the ectf h.110 specification requires that the t8110l must be powered from early power in hot swap applications. the circuit that generates the 0.7 v precharge voltage must also be powered from early power. refer to ectf h.110 and picmg compactpci ? hot swap specifications for hot swap requirements. 13.8.1 lpue (local pull-up enable) lpue is used as an assist in compactpci specifically for hot swap; see section 2.3.2 on page 20. during live board insertion/removal, the only devices which should be on early power are the power controller and interface parts (pci interface attached to j1, h.110 interface attached to j4). without the lpue, any device connected to the t8110l would get current flow from the early power through the pull-up resistors. when late power parts power up, they already have current flowing through the i/o and these devices could possibly latch up. the current flow is eliminated by lpue disabling the pull-up resistors. lpue is typically controlled by the power controller. the power controller will pull lpue low during board insertion/removal and will release lpue high so that the pull ups are re- enabled with late power turning on. signals that have pull-ups disabled by lpue are gp[7:0], fg[7:0], d[15:0], ld[31:0], lref[7:0], pri_ref_in, nr1_div_in, and nr2_div_in. 13.9 decoupling decoupling the t8110l v dd s with 0.1 f capacitors is recommended. 1000 pf or 0.01 f capacitors may be used in addition to the 0.1 f capacitors to provide additional decoupling. table 110. l_sc[3:0] and frame group rise and fall time parameter min typ max unit* l_scx rise time ? ? 5 ns l_scx fall time ? ? 4 ns frame group rise time ? ? 3 ns frame group fall time ? ? 3 ns
132 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics (continued) 13.10 apll v dd filter separate v dd s are provided for apll1 and apll2 for filtering purposes. v dd filtering will provide stability in the apll, primarily the vcos. an r/c low pass filter should be applied to the pll v dd s, see figure 30. depending on the quality of v dd and board layout characteristics, the r/c values should be selected to filter out unwanted fre- quencies above a targeted frequency. for example, a 25 ? resistor and 10 f capacitor will have a cut-off frequency of 636 hz. characterize the quality of your v dd and select component values accordingly. 25 ? is the maximum recommended resistor value. at high frequencies the esr of a bulk cap becomes a problem (no longer effectively low passes) so a high-frequency cap of 0.1 f or so is required to compensate for some of the higher clocks and various harmonics. this needs to be placed as close to the t8110l device as possible to minimize the radiational pick-up in the remaining trace length. apll1 and apll2 each draw approximately 7 ma at 3.3 v. hot swap applications can use late power to ensure the capacitance and in-rush current do not violate the picmg hot swap specification. 0995(f) figure 30. apll v dd filtering v ss t8110l apll1v dd v ss apll2v dd v dd = 3.3 v v dd = 3.3 v r c r c 0.1 f 0.1 f
agere systems inc. 133 data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 electrical characteristics (continued) 13.11 pc board pbga considerations the t8110l is a 272-ball plastic ball grid array package. the 16 centrally located thermal balls should be con- nected to board ground. while there are no special printed-circuit board requirements for the t8110l, there are specification requirements for pc board layout that must be adhered to. for instance, per the ectf h.110 specifi- cation, all ct bus data signals must not exceed 4 inches in length from connector to i/o cell and all ct bus clock signals must not exceed 2 inches in length from connector to i/o cell. we advise the customer to become familiar with applicable specifications for any pc board requirements. 13.12 unused pins multiple pins may share a common resistor. signals with pull-up/down resistors may be left unconnected if unused. unused 8 ma 3-state signals may be left unconnected. if xtal1_in and/or xtal2_in are being driven from an oscillator, then xtal1_out and/or xtal2_out must be left unconnected. if xtal2 is not used, xtal2_in should be pulled-up or tied directly to v dd and xtal2_out should be left unconnected. if vprecharge is unused, this signal may be left unconnected. all signals listed as no connect (d16, d20, e17, and g17) in table 8 must be left unconnected. 13.13 external pull-up pins the epu pins must be tied to an external pull-up resistor. multiple pins may share a common resistor. it is recom- mended that all epu pins be tied to a commmon 20 k ? pull-up resistor. 13.14 t8110l evaluation kits there is no t8110l-specific evaluation kit. if an evaluation kit is required, please purchase a t8110 pci evaluation kit, as the evaluation board allows the t8110 to be configured to be functionally identical to the t8110l. each kit contains an evaluation board, software, and documentation. the evaluation board is a full-length pci board and it includes the t8110 chip, a pci-to-local bus bridge, a dual t1/e1 line interface, a dual codec, and a dual slic. the software includes full source code, including rights to reuse. the documentation cd includes evaluation board schematics (orcad and .pdf formats), evaluation board bill of material (bom), and advisories. please refer to the website http://www.agere.com/enterprise_metro_access/tdm_interconnect.html for additional information. 13.15 t8110l ordering information table 111. t8110l ordering information device part number package comcode T-8110L---bal-db 272-ball pbga 700052229
134 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 package outline (continued) 13.15 pin and pad assignments (continued) 5-8906f(b). figure 31. t8110l pins by functional group vss vdd vdd vss vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss a b c d e f g h j k l m n p r t u v w y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 precharge gpio processor address processor control signals processor data reset pll pll local clock outputs local frame error signals (no connect) group data h-bus data h.110 clocks local reference inputs external clads/djats compatibility clocks pll mlac jtag port (xtal#1) (xtal#2) bist local pe h.100 pe h.110 pe thermal ground (n/c) vss epu epu v ss v ss vss (no connect) epu
agere systems inc. 135 data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 package outline (continued) 13.15 pin and pad assignments (continued) 5-4406 bottom view a b c d e f g h j k l m y n p r t u v w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 19 spaces @ 1.27 = 24.13 19 spaces @ 1.27 = 24.13 0.76 +0.14 ?0.16 a1 ball pad corner
136 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 13 package outline (continued) 13.15 pin and pad assignments (continued) 5-4406 side view 5-4406 top view 1.17 0.05 seating plane solder ball 0.60 0.10 0.20 0.36 +0.04 ?0.06 2.13 +0.19 ?0.21 27.00 24.00 +0.70 ?0.50 24.00 +0.70 ?0.50 a1 ball pad corner 27.00
agere systems inc. 137 data sheet february 2004 ambassador t8110l h.100/h.110 switch 14 jtag/boundary scan 14.1 the principle of boundary-scan architecture each primary input signal and primary output signal is supplemented with a multipurpose memory element called a boundary-scan cell. cells on device primary inputs are referred to as input cells and cells on primary outputs are referred to as output cells. input and output is relative to the core logic of the device. at any time, only one register can be connected from tdi to tdo. for example, instruction register (ir), bypass, boundary-scan, ident, or even some appropriate register internal to the core logic (see figure 32). the selected register is identified by the decoded output of the instruction register. certain instructions are mandatory, such as extest (boundary-scan register selected), whereas others are optional, such as the idcode instruction (ident register selected). figure 32. ieee ? 1149.1 boundary-scan architecture figure 32 shows the following elements: ! a set of four dedicated test pins, test data in (tdi), test mode select (tms), test clock (tck), test data out (tdo), and one optional test pin test reset (trstn). these pins are collectively referred to as the test access port (tap). ! a boundary-scan cell on each device?s primary input and primary output pin, connected internally to form a serial boundary-scan register (boundary scan). ! a finite-state machine tap controller with inputs tck and tms. ! an n-bit (n = 3) instruction register (ir), holding the current instruction. ! a 1-bit bypass register (bypass). ! an optional 32-bit identification register (ident) capable of being loaded with a permanent device identification code. internal core logic identification register instruction register (ir) test mode select test clock tms tck test reset (trstn) test data out tdo tdi test data in bypass tap controller
138 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch 14 jtag/boundary scan (continued) 14.1.1 instruction register the instruction register is 3 bits long and the capture value is 001. 14.2 boundary-scan register the t8110l boundary scan register is identical to that of the t8110 in the condition that the t8110?s vio/up_select pin is tied to ground. the only difference is that for the t8110l, this pin (u5) is internally tied to ground. please refer to the t8110 datasheet for the bit-to-pin assignment. table 112. instruction register instruction binary code description extest 000 places the boundary-scan register in extest mode. sample 001 places the boundary-scan register in sample mode. idcode 101 identification code. bypass 110, 111 places the bypass register in the scan chain. high z 010 places all outputs and i/os in 3-state mode.
agere systems inc. 139 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix a. constant and minimum delay connections a.1 connection definitions a forward connection is defined as one in which the output to time slot has a greater value than the input from time slot, or, put another way, the delta between them is positive. a reverse connection is defined as one in which the output to time slot has a lesser value than the input from time slot, and the delta between them is negative. for example, going from ts(1) to ts(38) is a forward connection, and the ts ? is +37, but going from ts(38) to ts(1) is a reverse connection, with a ts ? of ?37: where ts ? = ts( to ) ? ts( from ). similarly, a delta can be introduced for streams which will have a bearing in certain exceptions (discussed later): str ? = str( to ) ? str( from ). there is only one combination which forms a ts ? of +127 or ?127: ts ? = ts(127) ? ts(0) = +127, and ts ? = ts(0) ? ts(127) = ?127, but there are two combinations which form ts ? s of +126 or ?126: ts ? = ts(127) ? ts(1) = ts(126) ? ts(0) = +126, and ts ? = ts(1) ? ts(127) = ts(0) ? ts(126) = ?126, there are three combinations which yield +125 or ?125, and so on. the user can utilize the ts ? to control the latency of the resulting connection. in some cases, the latency must be minimized. in other cases, such as a block of connections which must maintain some relative integrity while cross- ing a frame boundary, the required latency of some of the connections may exceed a one frame (>128 time slots) to maintain the integrity of this virtual frame. the device uses a control bit at each connection memory location, vfc, for controlling latency, allowing each con- nection to select one of two alternating data buffers. a.2 delay type definitions constant delay ?this is a well-defined, predictable, and linear region of latency in which the to time slot is at least 128 time slots after the from time slot, but no more than 256 time slots after the from time slot. mathematically, constant delay latency is described as follows*, with l denoting latency, and vfc set to the value indicated: forward connections, vfc = 1: l = 128 + ts ? (0 ts ? 127) reverse connections, vfc = 0: l = 256 + ts ? (?127 ts ? ?1) example: switching from ts(37) to ts(1) as a constant delay, the delta is ?36, so fme is set to 0 and the result- ing latency is 256 ? 36 = 220 time slots. thus, the connection will be made from ts(37) of frame(n) to ts(1) of frame(n + 2). simple summary: use constant delay for latencies of 128 to 256 time slots, set vfc = 1 for forward connections, set vfc = 0 for reverse connections. * since ts ? = ts( to ) ?ts( from ), the user can modify the equations to solve for either ts( to ) or ts( from ).
140 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix a. constant and minimum delay connections (continued) a.2 delay type definitions (continued) figure 33. constant delay connection latency minimum delay ?this is the most common type of switching, but has a shorter range than constant delay, and the user must be aware of exceptions caused by interactions between the device's internal pipeline and the dual buff- ering. the to time slot is at least 3 time slots after the from time slot, but no more than 128 time slots after the from time slot. exceptions exist at ts ? s of +1, +2, ?126, and ?127. forward connections, vfc = 0: l = ts ? (3 ts ? 127). reverse connections, vfc = 1: l = 128 + ts ? (?125 ts ? 0). example: using the same switching from the example above, ts(37) to ts(1), the delta is ?36, so vfc is set to 1 to effect the minimum delay (setting to 0 effects constant delay), and the resulting latency is 128 ? 36 = 92 time slots. the relative positions of the end time slots are the same in both minimum and constant delay, i.e., they both switch to ts(1)], but the actual data is delayed by an additional frame in the constant delay case. simple summary: use minimum delay for latencies of 3 to 128 time slots, set vfc = 0 for forward connections, set vfc = 1 for reverse connections. exceptions to minimum delay ?up until this point in the discussion, the str ? s have not been discussed because the to and from streams have been irrelevant in the switching process. note: the one universally disallowed connection on the device is a ts ? of 0 and a str ? of 0. this is, of course, a stream + time-slot switching to itself! rather than try to list the exceptions mathematically, a table is provided. the latencies in these cases may exceed two frames due to the interaction of the intrinsic pipeline delays with the double buffering. applied delta (time slots) resulting latency ?127 128 0 127 255 256 (time slots) v f c = 0 v f c = 1 129
agere systems inc. 141 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix a. constant and minimum delay connections (continued) a.2 delay type definitions (continued) graphically, the minimum delay latency equations are illustrated below. the exceptions to the minimum delay have been included in the diagram, connected to the main function by dashed lines. 5-6224 figure 34. minimum delay connection latency lower stream rates ?the discussion has centered on 128 time-slot frames which correspond to 8.192 mbits/s data rates. how does one make similar predictions for lower stream rates? for 4.096 mbits/s, multiply the to and from time-slot values by two, i.e., time slot 0 at 4.096 mbits/s corresponds to time slot 0 at 8.192 mbits/s, and time slot 63 at 4.096 mbits/s corresponds to time slot 126 at 8.192 mbits/s. simi- larly, multiply values by four to convert 2.048 mbits/s values. the latency equations can then be applied directly. table 113. special cases (exceptions) vfc value ts ? latency for str ? < 0 latency for str ? 0 0 +1 257 257 0+2 258 2 1 ?126 258 2 1 ?127 257 257 applied delta (time slots) resulting latency ?127 0 127 127 128......256 (time slots) v f c = 1 v f c = 0 0 ?126 258 257 2 2 2 special long latency connections (see text)
142 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary key to using the table below: ! five character alphanumeric designation ! character 4 indicates the general register type as follows: ? divide = load value for divider ? enable = bit or bits to enable a function ? load = load value, typically for counter ? output = output only ? select = bit or bits select multiple functions ! character 5 indicates the size as follows: ? b = bit ? n = nibble ? p = partial register (2, 3, 5, 6, or 7 bits) ? r = register ! position column identifies the bit position in the register: ? 0, 1, 2, 3, 4, 5, 6, 7 for bits ? l for lower nibble ? u for upper nibble ? n-m for bit positions in a partial register
agere systems inc. 143 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name mnemonic description type register bit position aboen a and b clocks output enable 0x00220 u acrsn a clocks rate select 0x00223 l aioeb all i/o (master) enable 0x00103 7 bcrsn b clocks rate select 0x00223 u c2feb c2 fallback trigger enable 0x0010a 5 c2lob c2 latched error output 0x00122 5 c2tob c2 transient error output 0x00120 5 c2web c2 watchdog enable 0x0010e 5 c4feb /c4 fallback trigger enable 0x0010a 4 c4lob c4 latched error output 0x00122 4 c4tob c4 transient error output 0x00120 4 c4web /c4 watchdog enable 0x0010e 4 cafeb c8a fallback trigger enable 0x0010a 0 calob c8a latched error output 0x00122 0 catob c8a transient error output 0x00120 0 caweb c8a watchdog enable 0x0010e 0 cawsn c8a watchdog select 0x0010c l cbfeb c8b fallback trigger enable 0x0010a 1 cblob c8b latched error output 0x00122 1 cbtob c8b transient error output 0x00120 1 cbweb c8b watchdog enable 0x0010e 1 cbwsn c8b watchdog select 0x0010c u ccoen c clocks output enable 0x00220 l ccsen c clocks separate enable 0x00224 l cfbob fallback status output 0x00127 6 cfhln diag sync-to-frame high load 0x0014b l cfllr diag sync-to-frame low load 0x0014a ? cfpob clear_fallback pending output 0x00124 1 cfsen diag sync-to-frame en enable 0x0014b u cfsob failsafe status output 0x00127 7 ckmdr clock main divide 0x00201 ? ckmsr clock main select 0x00200 ? ckrdr clock resource divide 0x00205 ? cmfeb /c16? fallback trigger enable 0x0010a 3 cmlob /c16? latched error output 0x00122 3 cmtob /c16? transient error output 0x00120 3 cmweb /c16? watchdog enable 0x0010e 3 cpfeb /c16+ fallback trigger enable 0x0010a 2 cplob /c16+ latched error output 0x00122 2 cptob /c16+ transient error output 0x00120 2 cpweb /c16+ watchdog enable 0x0010e 2 csasr clock set access select 0x00106 ? d1feb dpll1 sync trigger enable 0x0010b 5 d1isr dpll1 input select 0x0020a ?
144 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name (continued) mnemonic description type register bit position d1lob dpll1 sync latched error output 0x00123 5 d1rsr dpll1 rate select 0x0020b ? d1tob dpll1 sync transient error output 0x00121 5 d1web dpll1 sync watchdog enable 0x0010f 5 d2feb dpll2 sync trigger enable 0x0010b 6 d2isr dpll2 input select 0x0020e ? d2lop dpll2 lock status output 0x00125 3:2 d2rsr dpll2 rate select 0x0020f ? d2tob dpll2 sync transient error output 0x00121 6 d2web dpll2 sync watchdog enable 0x0010f 6 dmmsp data memory mode select 0x00105 6:0 f0dsb fgio 0 r/w direction select 0x00482 0 f0iob fgio 0 data load 0x00480 0 f0isb frame 0 pulse inversion enable 0x00402 7 f0llr frame 0 lower start time load 0x00400 ? f0meb fgio 0 read mask enable 0x00481 0 f0rsr frame 0 pulse width rate select 0x00403 ? f0ulr frame 0 upper start time load 0x00401 ? f0wsp frame 0 pulse width select 0x00402 6:0 f1dsb fgio 1 r/w direction select 0x00482 1 f1iob fgio 1 data load 0x00480 1 f1isb frame 1 pulse inversion enable 0x00412 7 f1llr frame 1 lower start time load 0x00410 ? f1meb fgio 1 read mask enable 0x00481 1 f1rsr frame 1 pulse width rate select 0x00413 ? f1ulr frame 1 upper start time load 0x00411 ? f1wsp frame 1 pulse width select 0x00412 6:0 f2dsb fgio 2 r/w direction select 0x00482 2 f2iob fgio 2 data load 0x00480 2 f2isb frame 2 pulse inversion enable 0x00422 7 f2llr frame 2 lower start time load 0x00420 ? f2meb fgio 2 read mask enable 0x00481 2 f2rsr frame 2 pulse width rate select 0x00423 ? f2ulr frame 2 upper start time load 0x00421 ? f2wsp frame 2 pulse width select 0x00422 6:0 f3dsb fgio 3 r/w direction select 0x00482 3 f3iob fgio 3 data load 0x00480 3 f3isb frame 3 pulse inversion enable 0x00432 7 f3llr frame 3 lower start time load 0x00430 ? f3meb fgio 3 read mask enable 0x00481 3 f3rsr frame 3 pulse width rate select 0x00433 ? f3ulr frame 3 upper start time load 0x00431 ? f3wsp frame 3 pulse width select 0x00432 6:0
agere systems inc. 145 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name (continued) mnemonic description type register bit position f4dsb fgio 4 r/w direction select 0x00482 4 f4iob fgio 4 data load 0x00480 4 f4isb frame 4 pulse inversion enable 0x00442 7 f4llr frame 4 lower start time load 0x00440 ? f4meb fgio 4 read mask enable 0x00481 4 f4rsr frame 4 pulse width rate select 0x00443 ? f4ulr frame 4 upper start time load 0x00441 ? f4wsp frame 4 pulse width select 0x00442 6:0 f5dsb fgio 5 r/w direction select 0x00482 5 f5iob fgio 5 data load 0x00480 5 f5isb frame 5 pulse inversion enable 0x00452 7 f5llr frame 5 lower start time load 0x00450 ? f5meb fgio 5 read mask enable 0x00481 5 f5rsr frame 5 pulse width rate select 0x00453 ? f5ulr frame 5 upper start time load 0x00451 ? f5wsp frame 5 pulse width select 0x00452 6:0 f6dsb fgio 6 r/w direction select 0x00482 6 f6iob fgio 6 data load 0x00480 6 f6isb frame 6 pulse inversion enable 0x00462 7 f6llr frame 6 lower start time load 0x00460 ? f6meb fgio 6 read mask enable 0x00481 6 f6rsr frame 6 pulse width rate select 0x00463 ? f6ulr frame 6 upper start time load 0x00461 ? f6wsp frame 6 pulse width select 0x00462 6:0 f7dsb fgio 7 r/w direction select 0x00482 7 f7iob fgio 7 data load 0x00480 7 f7isb frame 7 pulse inversion enable 0x00472 7 f7llr frame 7 lower start time load 0x00470 ? f7meb fgio 7 read mask enable 0x00481 7 f7msr frame 7 mode select 0x00476 ? f7rsr frame 7 pulse width rate select 0x00473 ? f7ssp fg7 timer pulse shape select 0x00477 ? f7ulr frame 7 upper start time load 0x00471 ? f7wsn fg7 timer pulse width select 0x00477 l f7wsp frame 7 pulse width select 0x00472 6:0 fafeb /framea fallback trigger enable 0x0010b 0 falob /framea latched error output 0x00123 0 fatob /framea transient error output 0x00121 0 faweb /framea watchdog enable 0x0010f 0 fb1sb apll1 feedback reset select 0x00146 1 fb2sb apll2 feedback reset select 0x00146 2 fbcsr fallback control select 0x00108 ? fbfeb /frameb fallback trigger enable 0x0010b 1
146 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name (continued) mnemonic description type register bit position fbfob fallback enable status output 0x00124 7 fblob /frameb latched error output 0x00123 1 fbsop fallback states output 0x00124 6:4 fbtob /frameb transient error output 0x00121 1 fbweb /frameb watchdog enable 0x0010f 1 fcfeb /fr_comp fallback trigger enable 0x0010b 2 fcisb fg7 timer invert output select 0x00477 7 fcllr frame group 7 lower count load 0x00474 ? fclob /fr_comp latched error output 0x00123 2 fctob /fr_comp transient error output 0x00121 2 fculr frame group 7 upper count load 0x00475 ? fcweb /fr_comp watchdog enable 0x0010f 2 ffpob force_fallback pending output 0x00124 0 fgreb frame group enable 0x00103 5 fpasr frame phase alignment select 0x00107 ? frmsb diag /fr_comp input select 0x00145 4 frsen /fr_comp separate enable 0x00224 u frwsr /fr_comp width select 0x00222 ? fscsr failsafe return command select 0x00114 ? fseer failsafe enable enable 0x00115 ? fslob failsafe latched error output 0x00123 7 fsmsn fallback secondary mode select 0x00109 l fsssr failsafe sensitivity select 0x00116 ? fstob failsafe transient error output 0x00121 7 fsweb failsafe watchdog enable 0x0010f 7 ft0eb fg0 testpoint enable 0x00140 0 ft1eb fg1 testpoint enable 0x00140 1 ft2eb fg2 testpoint enable 0x00140 2 ft3eb fg3 testpoint enable 0x00140 3 ft4eb fg4 testpoint enable 0x00140 4 ft5eb fg5 testpoint enable 0x00140 5 ft6eb fg6 testpoint enable 0x00140 6 ft7eb fg7 testpoint enable 0x00140 7 ftpsr fg testpoint mux select 0x00141 ? ftrsn fallback type select 0x00109 u g0dsb gpio 0 r/w direction select 0x00502 0 g0iob gpio 0 data load 0x00500 0 g0meb gpio 0 read mask enable 0x00501 0 g0oeb gpio 0 override enable 0x00503 0 g1dsb gpio 1 r/w direction select 0x00502 1 g1iob gpio 1 data load 0x00500 1 g1meb gpio 1 read mask enable 0x00501 1 g1oeb gpio 0 override enable 0x00503 1
agere systems inc. 147 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name (continued) mnemonic description type register bit position g2dsb gpio 2 r/w direction select 0x00502 2 g2iob gpio 2 data load 0x00500 2 g2meb gpio 2 read mask enable 0x00501 2 g3dsb gpio 3 r/w direction select 0x00502 3 g3iob gpio 3 data load 0x00500 3 g3meb gpio 3 read mask enable 0x00501 3 g4dsb gpio 4 r/w direction select 0x00502 4 g4iob gpio 4 data load 0x00500 4 g4meb gpio 4 read mask enable 0x00501 4 g5dsb gpio 5 r/w direction select 0x00502 5 g5iob gpio 5 data load 0x00500 5 g5meb gpio 5 read mask enable 0x00501 5 g6dsb gpio 6 r/w direction select 0x00502 6 g6iob gpio 6 data load 0x00500 6 g6meb gpio 6 read mask enable 0x00501 6 g7dsb gpio 7 r/w direction select 0x00502 7 g7iob gpio 7 data load 0x00500 7 g7meb gpio 7 read mask enable 0x00501 7 gopob go clocks pending output 0x00124 2 gpieb general purpose i/o enable 0x00103 4 gsreb global subrate enable 0x00105 7 gt0eb gp0 testpoint enable 0x00142 0 gt1eb gp1 testpoint enable 0x00142 1 gt2eb gp2 testpoint enable 0x00142 2 gt3eb gp3 testpoint enable 0x00142 3 gt4eb gp4 testpoint enable 0x00142 4 gt5eb gp5 testpoint enable 0x00142 5 gt6eb gp6 testpoint enable 0x00142 6 gt7eb gp7 testpoint enable 0x00142 7 gtpsr gp testpoint mux select 0x00143 ? harsn h1x0 group a rate select 0x00300 l hbrsn h1x0 group b rate select 0x00300 u hckeb h1x0 clocks enable 0x00103 3 hcrsn h1x0 group c rate select 0x00301 l hdbeb h1x0 data bus enable 0x00103 2 hdrsn h1x0 group d rate select 0x00301 u hersn h1x0 group e rate select 0x00302 l hfrsn h1x0 group f rate select 0x00302 u hgrsn h1x0 group g rate select 0x00303 l hhrsn h1x0 group h rate select 0x00303 u hrbeb hard reset of back end enable 0x00101 1 iaslr diag, syserr assertion load 0x00149 ? icdsp diag, internal control mode select 0x00148 7:6
148 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name (continued) mnemonic description type register bit position icklp diag, internal control clkerr load 0x00148 5:4 icmsb invert clock main select 0x00204 4 idhor device id high output 0x0012b ? idlor device id low output 0x0012a ? iexlp diag, internal control exterr load 0x00148 1:0 if0sb invert interrupt fgio 0 select 0x00603 0 if1sb invert interrupt fgio 1 select 0x00603 1 if2sb invert interrupt fgio 2 select 0x00603 2 if3sb invert interrupt fgio 3 select 0x00603 3 if4sb invert interrupt fgio 4 select 0x00603 4 if5sb invert interrupt fgio 5 select 0x00603 5 if6sb invert interrupt fgio 6 select 0x00603 6 if7sb invert interrupt fgio 7 select 0x00603 7 ig0sb invert interrupt gpio 0 select 0x00607 0 ig1sb invert interrupt gpio 1 select 0x00607 1 ig2sb invert interrupt gpio 2 select 0x00607 2 ig3sb invert interrupt gpio 3 select 0x00607 3 ig4sb invert interrupt gpio 4 select 0x00607 4 ig5sb invert interrupt gpio 5 select 0x00607 5 ig6sb invert interrupt gpio 6 select 0x00607 6 ig7sb invert interrupt gpio 7 select 0x00607 7 ir0sb invert local reference 0 select 0x0020c 0 ir1sb invert local reference 1 select 0x0020c 1 ir2sb invert local reference 2 select 0x0020c 2 ir3sb invert local reference 3 select 0x0020c 3 ir4sb invert local reference 4 select 0x0020c 4 ir5sb invert local reference 5 select 0x0020c 5 ir6sb invert local reference 6 select 0x0020c 6 ir7sb invert local reference 7 select 0x0020c 7 isylp diag, internal control syserr load 0x00148 3:2 jamsr interrupt arbitration mode select 0x00610 ? jc0eb interrupt from clkerr 0 enable 0x0060e 0 jc0ob interrupt pending clkerr 0 output 0x0060c 0 jc1eb interrupt from clkerr 1 enable 0x0060e 1 jc1ob interrupt pending clkerr 1 output 0x0060c 1 jc2eb interrupt from clkerr 2 enable 0x0060e 2 jc2ob interrupt pending clkerr 2 output 0x0060c 2 jc3eb interrupt from clkerr 3 enable 0x0060e 3 jc3ob interrupt pending clkerr 3 output 0x0060c 3 jc4eb interrupt from clkerr 4 enable 0x0060e 4 jc4ob interrupt pending clkerr 4 output 0x0060c 4 jc5eb interrupt from clkerr 5 enable 0x0060e 5
agere systems inc. 149 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name (continued) mnemonic description type register bit position jc5ob interrupt pending clkerr 5 output 0x0060c 5 jc6eb interrupt from clkerr 6 enable 0x0060e 6 jc6ob interrupt pending clkerr 6 output 0x0060c 6 jc7eb interrupt from clkerr 7 enable 0x0060e 7 jc7ob interrupt pending clkerr 7 output 0x0060c 7 jc8eb interrupt from clkerr 8 enable 0x0060f 0 jc8ob interrupt pending clkerr 8 output 0x0060d 0 jc9eb interrupt from clkerr 9 enable 0x0060f 1 jc9ob interrupt pending clkerr 9 output 0x0060d 1 jcaeb interrupt from clkerr a enable 0x0060f 2 jcaob interrupt pending clkerr a output 0x0060d 2 jcbeb interrupt from clkerr b enable 0x0060f 3 jcbob interrupt pending clkerr b output 0x0060d 3 jcceb interrupt from clkerr c enable 0x0060f 4 jccob interrupt pending clkerr c output 0x0060d 4 jcdeb interrupt from clkerr d enable 0x0060f 5 jcdob interrupt pending clkerr d output 0x0060d 5 jceeb interrupt from clkerr e enable 0x0060f 6 jceob interrupt pending clkerr e output 0x0060d 6 jcfeb interrupt from clkerr f enable 0x0060f 7 jcfob interrupt pending clkerr f output 0x0060d 7 jcosr interrupt clkerr output mode select 0x00613 ? jcwsr interrupt clkerr pulse width select 0x00617 ? jf0eb interrupt from fgio 0 enable 0x00601 0 jf0ob interrupt pending fgio 0 output 0x00600 0 jf1eb interrupt from fgio 1 enable 0x00601 1 jf1ob interrupt pending fgio 1 output 0x00600 1 jf2eb interrupt from fgio 2 enable 0x00601 2 jf2ob interrupt pending fgio 2 output 0x00600 2 jf3eb interrupt from fgio 3 enable 0x00601 3 jf3ob interrupt pending fgio 3 output 0x00600 3 jf4eb interrupt from fgio 4 enable 0x00601 4 jf4ob interrupt pending fgio 4 output 0x00600 4 jf5eb interrupt from fgio 5 enable 0x00601 5 jf5ob interrupt pending fgio 5 output 0x00600 5 jf6eb interrupt from fgio 6 enable 0x00601 6 jf6ob interrupt pending fgio 6 output 0x00600 6 jf7eb interrupt from fgio 7 enable 0x00601 7 jf7ob interrupt pending fgio 7 output 0x00600 7 jg0eb interrupt from gpio 0 enable 0x00605 0 jg0ob interrupt pending gpio 0 output 0x00604 0 jg1eb interrupt from gpio 1 enable 0x00605 1 jg1ob interrupt pending gpio 1 output 0x00604 1 jg2eb interrupt from gpio 2 enable 0x00605 2
150 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name (continued) mnemonic description type register bit position jg2ob interrupt pending gpio 2 output 0x00604 2 jg3eb interrupt from gpio 3 enable 0x00605 3 jg3ob interrupt pending gpio 3 output 0x00604 3 jg4eb interrupt from gpio 4 enable 0x00605 4 jg4ob interrupt pending gpio 4 output 0x00604 4 jg5eb interrupt from gpio 5 enable 0x00605 5 jg5ob interrupt pending gpio 5 output 0x00604 5 jg6eb interrupt from gpio 6 enable 0x00605 6 jg6ob interrupt pending gpio 6 output 0x00604 6 jg7eb interrupt from gpio 7 enable 0x00605 7 jg7ob interrupt pending gpio 7 output 0x00604 7 jisor interrupt in-service output 0x006fc ? js0eb interrupt from syserr 0 enable 0x0060a 0 js0ob interrupt pending syserr 0 output 0x00608 0 js1eb interrupt from syserr 1 enable 0x0060a 1 js1ob interrupt pending syserr 1 output 0x00608 1 js2eb interrupt from syserr 2 enable 0x0060a 2 js2ob interrupt pending syserr 2 output 0x00608 2 js3eb interrupt from syserr 3 enable 0x0060a 3 js3ob interrupt pending syserr 3 output 0x00608 3 js4eb interrupt from syserr 4 enable 0x0060a 4 js4ob interrupt pending syserr 4 output 0x00608 4 js5eb interrupt from syserr 5 enable 0x0060a 5 js5ob interrupt pending syserr 5 output 0x00608 5 js6eb interrupt from syserr 6 enable 0x0060a 6 js6ob interrupt pending syserr 6 output 0x00608 6 js7eb interrupt from syserr 7 enable 0x0060a 7 js7ob interrupt pending syserr 7 output 0x00608 7 js8eb interrupt from syserr 8 enable 0x0060b 0 js8ob interrupt pending syserr 8 output 0x00609 0 js9eb interrupt from syserr 9 enable 0x0060b 1 js9ob interrupt pending syserr 9 output 0x00609 1 jsaeb interrupt from syserr a enable 0x0060b 2 jsaob interrupt pending syserr a output 0x00609 2 jsbeb interrupt from syserr b enable 0x0060b 3 jsbob interrupt pending syserr b output 0x00609 3 jsceb interrupt from syserr c enable 0x0060b 4 jscob interrupt pending syserr c output 0x00609 4 jsdeb interrupt from syserr d enable 0x0060b 5 jsdob interrupt pending syserr d output 0x00609 5 jseeb interrupt from syserr e enable 0x0060b 6 jseob interrupt pending syserr e output 0x00609 6 jsfeb interrupt from syserr f enable 0x0060b 7
agere systems inc. 151 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name (continued) mnemonic description type register bit position jsfob interrupt pending syserr f output 0x00609 7 jsosr interrupt syserr output mode select 0x00612 ? jswsr interrupt syserr pulse width select 0x00616 ? larsn local group a rate select 0x00320 l lbrsn local group b rate select 0x00320 u lc0sr local clock 0 output select 0x00228 ? lc1sr local clock 1 output select 0x00229 ? lc2sr local clock 2 output select 0x0022a ? lc3sr local clock 3 output select 0x0022b ? lckeb local clocks enable 0x00103 1 lcrsn local group c rate select 0x00321 l ldbeb local data bus enable 0x00103 0 ldrsn local group d rate select 0x00321 u lersn local group e rate select 0x00322 l lfrsn local group f rate select 0x00322 u lgrsn local group g rate select 0x00323 l lhrsn local group h rate select 0x00323 u lrisr local reference input select 0x00208 ? n1dsb nr1 divider inversion select 0x00204 1 n1dsn netref1 divider input select 0x00210 u n1feb netref1 fallback trigger enable 0x0010b 3 n1isn netref1 main input select 0x00210 l n1lob netref1 latched error output 0x00123 3 n1lsr netref1 local reference select 0x00212 ? n1oen netref1 output enable 0x00221 l n1ssb nr1 selector inversion select 0x00204 0 n1tob netref1 transient error output 0x00121 3 n1web netref1 watchdog enable 0x0010f 3 n1wsn netref1 watchdog select 0x0010d l n2dsb nr2 divider inversion select 0x00204 3 n2dsn netref1 divider input select 0x00214 u n2feb netref2 fallback trigger enable 0x0010b 4 n2isn netref1 main input select 0x00214 l n2lob netref2 latched error output 0x00123 4 n2lsr netref1 local reference select 0x00216 ? n2oen netref1 output enable 0x00221 u n2ssb nr2 selector inversion select 0x00204 2 n2tob netref2 transient error output 0x00121 4 n2web netref2 watchdog enable 0x0010f 4 n2wsn netref2 watchdog select 0x0010d u
152 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 114. mnemonic summary, sorted by name (continued) mnemonic description type register bit position nr1dr netref1 divide 0x00211 ? nr2dr netref2 divide 0x00215 ? olhlr out-of-lock threshold, high load 0x00119 ? olllr out-of-lock threshold, low load 0x00118 ? ooler out-of-lock monitor enable 0x0011a ? oolob out-of-lock status output 0x00125 6 p1isr apll1 input select 0x00202 ? p1rsr apll1 rate select 0x00203 ? p2rsr apll2 rate select 0x00207 ? pafsr phase align frame enable 0x00107 ? s2feb /sclkx2 fallback trigger enable 0x0010a 7 s2lob /sclkx2 latched error output 0x00122 7 s2tob /sclkx2 transient error output 0x00120 7 s2web /sclkx2 watchdog enable 0x0010e 7 scfeb sclk fallback trigger enable 0x0010a 6 sclob sclk latched error output 0x00122 6 sclsb diag state counter mode en select 0x00145 3 scmlr diag state counter mode low load 0x00144 ? scmsb diag state counter carry select 0x00145 5 scrsr sclk/sclkx2 rate select 0x00227 ? sctob sclk transient error output 0x00120 6 sculp diag state counter mode high load 0x00145 2:0 scweb sclk watchdog enable 0x0010e 6 srbeb soft reset of back end enable 0x00101 0 sresr soft reset select 0x00100 ? tcosr t clock output select 0x00226 ? veror version id register output 0x00128 ? xysob active clock set output 0x00124 3
agere systems inc. 153 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register mnemonic description type register bit position sresr soft reset select 0x00100 ? srbeb soft reset of back end enable 0x00101 0 hrbeb hard reset of back end enable 0x00101 1 ldbeb local data bus enable 0x00103 0 lckeb local clocks enable 0x00103 1 hdbeb h1x0 data bus enable 0x00103 2 hckeb h1x0 clocks enable 0x00103 3 gpieb general-purpose i/o enable 0x00103 4 fgreb frame group enable 0x00103 5 aioeb all i/o (master) enable 0x00103 7 gsreb global subrate enable 0x00105 7 dmmsp data memory mode select 0x00105 6:0 csasr clock set access select 0x00106 ? fpasr frame phase alignment select 0x00107 ? pafsr phase align frame enable 0x00107 ? fbcsr fallback control select 0x00108 ? fsmsn fallback secondary mode select 0x00109 l ftrsn fallback type select 0x00109 u cafeb c8a fallback trigger enable 0x0010a 0 cbfeb c8b fallback trigger enable 0x0010a 1 cpfeb /c16+ fallback trigger enable 0x0010a 2 cmfeb /c16? fallback trigger enable 0x0010a 3 c4feb /c4 fallback trigger enable 0x0010a 4 c2feb c2 fallback trigger enable 0x0010a 5 scfeb sclk fallback trigger enable 0x0010a 6 s2feb /sclkx2 fallback trigger enable 0x0010a 7 fafeb /framea fallback trigger enable 0x0010b 0 fbfeb /frameb fallback trigger enable 0x0010b 1 fcfeb /fr_comp fallback trigger enable 0x0010b 2 n1feb netref1 fallback trigger enable 0x0010b 3 n2feb netref2 fallback trigger enable 0x0010b 4 d1feb dpll1 sync trigger enable 0x0010b 5 d2feb dpll2 sync trigger enable 0x0010b 6 cawsn c8a watchdog select 0x0010c l cbwsn c8b watchdog select 0x0010c u n1wsn netref1 watchdog select 0x0010d l n2wsn netref2 watchdog select 0x0010d u caweb c8a watchdog enable 0x0010e 0 cbweb c8b watchdog enable 0x0010e 1 cpweb /c16+ watchdog enable 0x0010e 2
154 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register (continued) mnemonic description type register bit position cmweb /c16? watchdog enable 0x0010e 3 c4web /c4 watchdog enable 0x0010e 4 c2web c2 watchdog enable 0x0010e 5 scweb sclk watchdog enable 0x0010e 6 s2web /sclkx2 watchdog enable 0x0010e 7 faweb /framea watchdog enable 0x0010f 0 fbweb /frameb watchdog enable 0x0010f 1 fcweb /fr_comp watchdog enable 0x0010f 2 n1web netref1 watchdog enable 0x0010f 3 n2web netref2 watchdog enable 0x0010f 4 d1web dpll1 sync watchdog enable 0x0010f 5 d2web dpll2 sync watchdog enable 0x0010f 6 fsweb failsafe watchdog enable 0x0010f 7 fscsr failsafe return command select 0x00114 ? fseer failsafe enable enable 0x00115 ? fsssr failsafe sensitivity select 0x00116 ? olllr out-of-lock threshold, low load 0x00118 ? olhlr out-of-lock threshold, high load 0x00119 ? ooler out-of-lock monitor enable 0x0011a ? catob c8a transient error output 0x00120 0 cbtob c8b transient error output 0x00120 1 cptob /c16+ transient error output 0x00120 2 cmtob /c16? transient error output 0x00120 3 c4tob c4 transient error output 0x00120 4 c2tob c2 transient error output 0x00120 5 sctob sclk transient error output 0x00120 6 s2tob /sclkx2 transient error output 0x00120 7 fatob /framea transient error output 0x00121 0 fbtob /frameb transient error output 0x00121 1 fctob /fr_comp transient error output 0x00121 2 n1tob netref1 transient error output 0x00121 3 n2tob netref2 transient error output 0x00121 4 d1tob dpll1 sync transient error output 0x00121 5 d2tob dpll2 sync transient error output 0x00121 6 fstob failsafe transient error output 0x00121 7 calob c8a latched error output 0x00122 0 cblob c8b latched error output 0x00122 1 cplob /c16+ latched error output 0x00122 2 cmlob /c16? latched error output 0x00122 3 c4lob c4 latched error output 0x00122 4 c2lob c2 latched error output 0x00122 5 sclob sclk latched error output 0x00122 6 s2lob /sclkx2 latched error output 0x00122 7 falob /framea latched error output 0x00123 0
agere systems inc. 155 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register (continued) mnemonic description type register bit position fblob /frameb latched error output 0x00123 1 fclob /fr_comp latched error output 0x00123 2 n1lob netref1 latched error output 0x00123 3 n2lob netref2 latched error output 0x00123 4 d1lob dpll1 sync latched error output 0x00123 5 d2lob dpll2 sync latched error output 0x00123 6 fslob failsafe latched error output 0x00123 7 ffpob force_fallback pending output 0x00124 0 cfpob clear_fallback pending output 0x00124 1 gopob go clocks pending output 0x00124 2 xysob active clock set output 0x00124 3 fbfob fallback enable status output 0x00124 7 fbsop fallback states output 0x00124 6:4 cfbob fallback status output 0x00127 6 cfsob failsafe status output 0x00127 7 veror version id register output 0x00128 ? idlor device id low output 0x0012a ? idhor device id high output 0x0012b ? ft0eb fg0 testpoint enable 0x00140 0 ft1eb fg1 testpoint enable 0x00140 1 ft2eb fg2 testpoint enable 0x00140 2 ft3eb fg3 testpoint enable 0x00140 3 ft4eb fg4 testpoint enable 0x00140 4 ft5eb fg5 testpoint enable 0x00140 5 ft6eb fg6 testpoint enable 0x00140 6 ft7eb fg7 testpoint enable 0x00140 7 ftpsr fg testpoint mux select 0x00141 ? gt0eb gp0 testpoint enable 0x00142 0 gt1eb gp1 testpoint enable 0x00142 1 gt2eb gp2 testpoint enable 0x00142 2 gt3eb gp3 testpoint enable 0x00142 3 gt4eb gp4 testpoint enable 0x00142 4 gt5eb gp5 testpoint enable 0x00142 5 gt6eb gp6 testpoint enable 0x00142 6 gt7eb gp7 testpoint enable 0x00142 7 gtpsr gp testpoint mux select 0x00143 ? scmlr diagnostic, state counter mode low load 0x00144 ? sclsb diagnostic, state counter mode en select 0x00145 3 frmsb diagnostic, /fr_comp input select 0x00145 4 scmsb diagnostic, state counter carry select 0x00145 5 sculp diagnostic, state counter mode high load 0x00145 2:0 fb1sb apll1 feedback reset select 0x00146 1
156 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register (continued) mnemonic description type register bit position fb2sb apll2 feedback reset select 0x00146 2 iexlp diagnostic, interrupt control exterr load 0x00148 1:0 isylp diagnostic, interrupt control syserr load 0x00148 3:2 icklp diagnostic, interrupt control clkerr load 0x00148 5:4 icdsp diagnostic, interrupt control mode select 0x00148 7:6 iaslr diagnostic, syserr assertion load 0x00149 ? cfllr diagnostic sync-to-frame low load 0x0014a ? cfhln diagnostic sync-to-frame high load 0x0014b l cfsen diagnostic sync-to-frame en enable 0x0014b u ckmsr clock main select 0x00200 ? ckmdr clock main divide 0x00201 ? p1isr apll1 input select 0x00202 ? p1rsr apll1 rate select 0x00203 ? n1ssb nr1 selector inversion select 0x00204 0 n1dsb nr1 divider inversion select 0x00204 1 n2ssb nr2 selector inversion select 0x00204 2 n2dsb nr2 divider inversion select 0x00204 3 icmsb invert clock main select 0x00204 4 ckrdr clock resource divide 0x00205 ? p2rsr apll2 rate select 0x00207 ? lrisr local reference input select 0x00208 ? d1isr dpll1 input select 0x0020a ? d1rsr dpll1 rate select 0x0020b ? ir0sb invert local reference 0 select 0x0020c 0 ir1sb invert local reference 1 select 0x0020c 1 ir2sb invert local reference 2 select 0x0020c 2 ir3sb invert local reference 3 select 0x0020c 3 ir4sb invert local reference 4 select 0x0020c 4 ir5sb invert local reference 5 select 0x0020c 5 ir6sb invert local reference 6 select 0x0020c 6 ir7sb invert local reference 7 select 0x0020c 7 d2isr dpll2 input select 0x0020e ? d2rsr dpll2 rate select 0x0020f ? n1isn netref1 main input select 0x00210 l n1dsn netref1 divider input select 0x00210 u nr1dr netref1 divide 0x00211 ? n1lsr netref1 local reference select 0x00212 ? n2isn netref1 main input select 0x00214 l n2dsn netref1 divider input select 0x00214 u nr2dr netref2 divide 0x00215 ? n2lsr netref1 local reference select 0x00216 ? ccoen c clocks output enable 0x00220 l
agere systems inc. 157 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register (continued) mnemonic description type register bit position aboen a and b clocks output enable 0x00220 u n1oen netref1 output enable 0x00221 l n2oen netref1 output enable 0x00221 u frwsr /fr_comp width select 0x00222 ? acrsn a clocks rate select 0x00223 l bcrsn b clocks rate select 0x00223 u ccsen c clocks separate enable 0x00224 l frsen /fr_comp separate enable 0x00224 u tcosr t clock output select 0x00226 ? scrsr sclk/sclkx2 rate select 0x00227 ? lc0sr local clock 0 output select 0x00228 ? lc1sr local clock 1 output select 0x00229 ? lc2sr local clock 2 output select 0x0022a ? lc3sr local clock 3 output select 0x0022b ? harsn h1x0 group a rate select 0x00300 l hbrsn h1x0 group b rate select 0x00300 u hcrsn h1x0 group c rate select 0x00301 l hdrsn h1x0 group d rate select 0x00301 u hersn h1x0 group e rate select 0x00302 l hfrsn h1x0 group f rate select 0x00302 u hgrsn h1x0 group g rate select 0x00303 l hhrsn h1x0 group h rate select 0x00303 u larsn local group a rate select 0x00320 l lbrsn local group b rate select 0x00320 u lcrsn local group c rate select 0x00321 l ldrsn local group d rate select 0x00321 u lersn local group e rate select 0x00322 l lfrsn local group f rate select 0x00322 u lgrsn local group g rate select 0x00323 l lhrsn local group h rate select 0x00323 u f0llr frame 0 lower start time load 0x00400 ? f0ulr frame 0 upper start time load 0x00401 ? f0isb frame 0 pulse inversion enable 0x00402 7 f0wsp frame 0 pulse width select 0x00402 6:0 f0rsr frame 0 pulse width rate select 0x00403 ? f1llr frame 1 lower start time load 0x00410 ? f1ulr frame 1 upper start time load 0x00411 ? f1isb frame 1 pulse inversion enable 0x00412 7 f1wsp frame 1 pulse width select 0x00412 6:0 f1rsr frame 1 pulse width rate select 0x00413 ? f2llr frame 2 lower start time load 0x00420 ? f2ulr frame 2 upper start time load 0x00421 ? f2isb frame 2 pulse inversion enable 0x00422 7
158 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register (continued) mnemonic description type register bit position f2wsp frame 2 pulse width select 0x00422 6:0 f2rsr frame 2 pulse width rate select 0x00423 ? f3llr frame 3 lower start time load 0x00430 ? f3ulr frame 3 upper start time load 0x00431 ? f3isb frame 3 pulse inversion enable 0x00432 7 f3wsp frame 3 pulse width select 0x00432 6:0 f3rsr frame 3 pulse width rate select 0x00433 ? f4llr frame 4 lower start time load 0x00440 ? f4ulr frame 4 upper start time load 0x00441 ? f4isb frame 4 pulse inversion enable 0x00442 7 f4wsp frame 4 pulse width select 0x00442 6:0 f4rsr frame 4 pulse width rate select 0x00443 ? f5llr frame 5 lower start time load 0x00450 ? f5ulr frame 5 upper start time load 0x00451 ? f5isb frame 5 pulse inversion enable 0x00452 7 f5wsp frame 5 pulse width select 0x00452 6:0 f5rsr frame 5 pulse width rate select 0x00453 ? f6llr frame 6 lower start time load 0x00460 ? f6ulr frame 6 upper start time load 0x00461 ? f6isb frame 6 pulse inversion enable 0x00462 7 f6wsp frame 6 pulse width select 0x00462 6:0 f6rsr frame 6 pulse width rate select 0x00463 ? f7llr frame 7 lower start time load 0x00470 ? f7ulr frame 7 upper start time load 0x00471 ? f7isb frame 7 pulse inversion enable 0x00472 7 f7wsp frame 7 pulse width select 0x00472 6:0 f7rsr frame 7 pulse width rate select 0x00473 ? fcllr frame group 7 lower count load 0x00474 ? fculr frame group 7 upper count load 0x00475 ? f7msr frame 7 mode select 0x00476 ? fcisb fg7 timer invert output select 0x00477 7 f7wsn fg7 timer pulse width select 0x00477 l f7ssp fg7 timer pulse shape select 0x00477 ? f0iob fgio 0 data load 0x00480 0 f1iob fgio 1 data load 0x00480 1 f2iob fgio 2 data load 0x00480 2 f3iob fgio 3 data load 0x00480 3 f4iob fgio 4 data load 0x00480 4 f5iob fgio 5 data load 0x00480 5 f6iob fgio 6 data load 0x00480 6 f7iob fgio 7 data load 0x00480 7 f0meb fgio 0 read mask enable 0x00481 0 f1meb fgio 1 read mask enable 0x00481 1 f2meb fgio 2 read mask enable 0x00481 2
agere systems inc. 159 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register (continued) mnemonic description type register bit position f3meb fgio 3 read mask enable 0x00481 3 f4meb fgio 4 read mask enable 0x00481 4 f5meb fgio 5 read mask enable 0x00481 5 f6meb fgio 6 read mask enable 0x00481 6 f7meb fgio 7 read mask enable 0x00481 7 f0dsb fgio 0 r/w direction select 0x00482 0 f1dsb fgio 1 r/w direction select 0x00482 1 f2dsb fgio 2 r/w direction select 0x00482 2 f3dsb fgio 3 r/w direction select 0x00482 3 f4dsb fgio 4 r/w direction select 0x00482 4 f5dsb fgio 5 r/w direction select 0x00482 5 f6dsb fgio 6 r/w direction select 0x00482 6 f7dsb fgio 7 r/w direction select 0x00482 7 g0iob gpio 0 data load 0x00500 0 g1iob gpio 1 data load 0x00500 1 g2iob gpio 2 data load 0x00500 2 g3iob gpio 3 data load 0x00500 3 g4iob gpio 4 data load 0x00500 4 g5iob gpio 5 data load 0x00500 5 g6iob gpio 6 data load 0x00500 6 g7iob gpio 7 data load 0x00500 7 g0meb pio 0 read mask enable 0x00501 0 g1meb gpio 1 read mask enable 0x00501 1 g2meb gpio 2 read mask enable 0x00501 2 g3meb gpio 3 read mask enable 0x00501 3 g4meb gpio 4 read mask enable 0x00501 4 g5meb gpio 5 read mask enable 0x00501 5 g6meb gpio 6 read mask enable 0x00501 6 g7meb gpio 7 read mask enable 0x00501 7 g0dsb gpio 0 r/w direction select 0x00502 0 g1dsb gpio 1 r/w direction select 0x00502 1 g2dsb gpio 2 r/w direction select 0x00502 2 g3dsb gpio 3 r/w direction select 0x00502 3 g4dsb gpio 4 r/w direction select 0x00502 4 g5dsb gpio 5 r/w direction select 0x00502 5 g6dsb gpio 6 r/w direction select 0x00502 6 g7dsb gpio 7 r/w direction select 0x00502 7 g0oeb gpio 0 override enable 0x00503 0 g1oeb gpio 1 override enable 0x00503 1 jf0ob interrupt pending fgio 0 output 0x00600 0 jf1ob interrupt pending fgio 1 output 0x00600 1 jf2ob interrupt pending fgio 2 output 0x00600 2 jf3ob interrupt pending fgio 3 output 0x00600 3 jf4ob interrupt pending fgio 4 output 0x00600 4
160 160 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register (continued) mnemonic description type register bit position jf5ob interrupt pending fgio 5 output 0x00600 5 jf6ob interrupt pending fgio 6 output 0x00600 6 jf7ob interrupt pending fgio 7 output 0x00600 7 jf0eb interrupt from fgio 0 enable 0x00601 0 jf1eb interrupt from fgio 1 enable 0x00601 1 jf2eb interrupt from fgio 2 enable 0x00601 2 jf3eb interrupt from fgio 3 enable 0x00601 3 jf4eb interrupt from fgio 4 enable 0x00601 4 jf5eb interrupt from fgio 5 enable 0x00601 5 jf6eb interrupt from fgio 6 enable 0x00601 6 jf7eb interrupt from fgio 7 enable 0x00601 7 if0sb invert interrupt fgio 0 select 0x00603 0 if1sb invert interrupt fgio 1 select 0x00603 1 if2sb invert interrupt fgio 2 select 0x00603 2 if3sb invert interrupt fgio 3 select 0x00603 3 if4sb invert interrupt fgio 4 select 0x00603 4 if5sb invert interrupt fgio 5 select 0x00603 5 if6sb invert interrupt fgio 6 select 0x00603 6 if7sb invert interrupt fgio 7 select 0x00603 7 jg0ob interrupt pending gpio 0 output 0x00604 0 jg1ob interrupt pending gpio 1 output 0x00604 1 jg2ob interrupt pending gpio 2 output 0x00604 2 jg3ob interrupt pending gpio 3 output 0x00604 3 jg4ob interrupt pending gpio 4 output 0x00604 4 jg5ob interrupt pending gpio 5 output 0x00604 5 jg6ob interrupt pending gpio 6 output 0x00604 6 jg7ob interrupt pending gpio 7 output 0x00604 7 jg0eb interrupt from gpio 0 enable 0x00605 0 jg1eb interrupt from gpio 1 enable 0x00605 1 jg2eb interrupt from gpio 2 enable 0x00605 2 jg3eb interrupt from gpio 3 enable 0x00605 3 jg4eb interrupt from gpio 4 enable 0x00605 4 jg5eb interrupt from gpio 5 enable 0x00605 5 jg6eb interrupt from gpio 6 enable 0x00605 6 jg7eb interrupt from gpio 7 enable 0x00605 7 ig0sb invert interrupt gpio 0 select 0x00607 0 ig1sb invert interrupt gpio 1 select 0x00607 1 ig2sb invert interrupt gpio 2 select 0x00607 2 ig3sb invert interrupt gpio 3 select 0x00607 3 ig4sb invert interrupt gpio 4 select 0x00607 4 ig5sb invert interrupt gpio 5 select 0x00607 5 ig6sb invert interrupt gpio 6 select 0x00607 6 ig7sb invert interrupt gpio 7 select 0x00607 7
agere systems inc. 161 data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register (continued) mnemonic description type register bit position js0ob interrupt pending syserr 0 output 0x00608 0 js1ob interrupt pending syserr 1 output 0x00608 1 js2ob interrupt pending syserr 2 output 0x00608 2 js3ob interrupt pending syserr 3 output 0x00608 3 js4ob interrupt pending syserr 4 output 0x00608 4 js5ob interrupt pending syserr 5 output 0x00608 5 js6ob interrupt pending syserr 6 output 0x00608 6 js7ob interrupt pending syserr 7 output 0x00608 7 js8ob interrupt pending syserr 8 output 0x00609 0 js9ob interrupt pending syserr 9 output 0x00609 1 jsaob interrupt pending syserr a output 0x00609 2 jsbob interrupt pending syserr b output 0x00609 3 jscob interrupt pending syserr c output 0x00609 4 jsdob interrupt pending syserr d output 0x00609 5 jseob interrupt pending syserr e output 0x00609 6 jsfob interrupt pending syserr f output 0x00609 7 js0eb interrupt from syserr 0 enable 0x0060a 0 js1eb interrupt from syserr 1 enable 0x0060a 1 js2eb interrupt from syserr 2 enable 0x0060a 2 js3eb interrupt from syserr 3 enable 0x0060a 3 js4eb interrupt from syserr 4 enable 0x0060a 4 js5eb interrupt from syserr 5 enable 0x0060a 5 js6eb interrupt from syserr 6 enable 0x0060a 6 js7eb interrupt from syserr 7 enable 0x0060a 7 js8eb interrupt from syserr 8 enable 0x0060b 0 js9eb interrupt from syserr 9 enable 0x0060b 1 jsaeb interrupt from syserr a enable 0x0060b 2 jsbeb interrupt from syserr b enable 0x0060b 3 jsceb interrupt from syserr c enable 0x0060b 4 jsdeb interrupt from syserr d enable 0x0060b 5 jseeb interrupt from syserr e enable 0x0060b 6 jsfeb interrupt from syserr f enable 0x0060b 7 jc0ob interrupt pending clkerr 0 output 0x0060c 0 jc1ob interrupt pending clkerr 1 output 0x0060c 1 jc2ob interrupt pending clkerr 2 output 0x0060c 2 jc3ob interrupt pending clkerr 3 output 0x0060c 3 jc4ob interrupt pending clkerr 4 output 0x0060c 4 jc5ob interrupt pending clkerr 5 output 0x0060c 5 jc6ob interrupt pending clkerr 6 output 0x0060c 6 jc7ob interrupt pending clkerr 7 output 0x0060c 7 jc8ob interrupt pending clkerr 8 output 0x0060d 0 jc9ob interrupt pending clkerr 9 output 0x0060d 1 jcaob interrupt pending clkerr a output 0x0060d 2
162 162 agere systems inc. data sheet february 2004 ambassador t8110l h.100/h.110 switch appendix b. register bit field mnemonic summary (continued) table 115. mnemonic summary, sorted by register (continued) mnemonic description type register bit position jcbob interrupt pending clkerr b output 0x0060d 3 jccob interrupt pending clkerr c output 0x0060d 4 jcdob interrupt pending clkerr d output 0x0060d 5 jceob interrupt pending clkerr e output 0x0060d 6 jcfob interrupt pending clkerr f output 0x0060d 7 jc0eb interrupt from clkerr 0 enable 0x0060e 0 jc1eb interrupt from clkerr 1 enable 0x0060e 1 jc2eb interrupt from clkerr 2 enable 0x0060e 2 jc3eb interrupt from clkerr 3 enable 0x0060e 3 jc4eb interrupt from clkerr 4 enable 0x0060e 4 jc5eb interrupt from clkerr 5 enable 0x0060e 5 jc6eb interrupt from clkerr 6 enable 0x0060e 6 jc7eb interrupt from clkerr 7 enable 0x0060e 7 jc8eb interrupt from clkerr 8 enable 0x0060f 0 jc9eb interrupt from clkerr 9 enable 0x0060f 1 jcaeb interrupt from clkerr a enable 0x0060f 2 jcbeb interrupt from clkerr b enable 0x0060f 3 jcceb interrupt from clkerr c enable 0x0060f 4 jcdeb interrupt from clkerr d enable 0x0060f 5 jceeb interrupt from clkerr e enable 0x0060f 6 jcfeb interrupt from clkerr f enable 0x0060f 7 jamsr interrupt arbitration mode select 0x00610 ? jsosr interrupt syserr output mode select 0x00612 ? jcosr interrupt clkerr output mode select 0x00613 ? jswsr interrupt syserr pulse width select 0x00616 ? jcwsr interrupt clkerr pulse width select 0x00617 ? jisor interrupt in-service output 0x006fc ?
agere systems inc. 163 data sheet february 2004 ambassador t8110l h.100/h.110 switch significant changes between the june 2003 and november 2003 release changes that were made to this document (since revision 3) are listed below. table 116. changes page description page 11 added pen, testmode interface signals to table 6. page 17 added pen, testmode pins to table 8. page 126 added thermal parameters definitions and values. page 133 removed signals listed as no connects. page 141 changed boundary of constant delay rev connections.
copyright ? 2004 agere systems inc. all rights reserved february 2004 ds04-024swch (replaces ds03-132swch and ay03-020swch) agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, the agere logo are trademarks and ambassador is a registered trademark of agere systems inc. for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, room 10a-301c, 1110 american parkway ne, allentown, pa 18109-91386 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-54614688 (shanghai), (86) 755-25881122 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045 motorola is a registered trademark of motorola, inc. intel is a registered trademark of intel corporation. at&t is a registered trademark of at&t corporation. compactpci is a registered trademark of the pci industrial computer manufacturers group. mvip is a trademark of natural microsystems corporation. ieee is a registered trademark of the institute of electrical and electronic engineers, inc.

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